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EVAL-AD1896EB 参数 Datasheet PDF下载

EVAL-AD1896EB图片预览
型号: EVAL-AD1896EB
PDF下载: 下载PDF文件 查看货源
内容描述: AD1896 7.75 : 1到1 : 8 , 192千赫立体声ASRC评估板 [AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board]
分类和应用:
文件页数/大小: 28 页 / 534 K
品牌: AD [ ANALOG DEVICES ]
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EVAL-AD1896EB
DEFAULT SETUP
AD1852 DAC
U12
256f
S
MCLK_I
SCLK_I
LEFT OUT
f
S_IN
SET EXTERNALLY
f
S_OUT
44.1kHz
LRCLK_I
SDATA_I
RIGHT OUT
INPUT DATA:
DIRECT DIGITAL INPUT HEADER
HDR3 (DDI)
SCLK
LRCLK
SDATA
AD1896
U13
SCLK_I
SCLK_O
OUTPUT DATA:
DIRECT DIGITAL OUTPUT HEADER
HDR5 (DDO)
SCLK
LRCLK
SDATA
LRCLK_I LRCLK_O
SDATA_I
MCLK_I
1
2 3
33.868MHz CRYSTAL
SDATA_O
MCLK_O
CS8404 DIT
U6
SDATA_I
LRCLK_I
SCLK_I
128
f
S
MCLK_I
SPDIF OUTPUT
JUMPER JP4
CLOCK DIVIDER
256
f
S
128
f
S
Figure 3. Default Setup (Refer to Figure 5 for Detailed Setup)
TYPICAL PERFORMANCE
Typical performance of the AD1896 for 44.1 kHz:48 kHz (asynchronous) sample rate is listed below.
1.
2.
3.
4.
DNR, No Filter
DNR, A-Weighted
THD+N, No Filter
Frequency Response
–139 dBFS, 20 Hz to 20 kHz (–60 dBFS)
–142 dBFS, 20 Hz to 20 kHz (–60 dBFS)
–120 dBFS, 20 Hz to 20 kHz (0 dBFS)
±
0.015 dB, 20 Hz to 20 kHz (0 dBFS)
Table IX. MCLK_I Frequencies for Common Sample Rates in Master Mode
Sample Rate (kHz)
44.100
48.000
96.000
256
MCLK_I Frequency (MHz)
f
S
512 f
S
768
22.579200
24.576000
f
S
11.289600
12.288000
24.576000
33.868800
EXTERNAL 192 kHz CLOCK GENERATOR CIRCUIT
An external circuit can be used to generate the 192 kHz clock
signals (SCLK, LRCLK) using on-board 128 f
S
clock oscilla-
tor (U15) running at 24.576 MHz. Please refer to Figure 4 for
the schematic and instructions on how to connect the exter-
nal circuit to the AD1896EB. In general, external SCLK and
LRCLK can be used for converting the audio input data to 192 kHz
rate by connecting SCLK to SCLK_O (DDO_SCLK_O,
HDR5 on the AD1896EB) and LRCLK to LRCLK_O
(DDO_LRCLK_O, HDR5 on the AD1896EB). On-board SPDIF
transmitter CS8404 (U6) does not support sample rates above
96 kHz.
ATTACHMENTS
Appendix A
1. External 192 kHz Clock Generator Circuit
2. AD1896 Evaluation Board Block Diagram, Schematics, and
Layout Plots
3. Bill of Materials
4. PLD Code
FURTHER INFORMATION
Ordering Information
Order number is EVAL-AD1896EB
For Application Questions or Technical Support
Contact Analog Devices’ Central Applications Department at
1-781-937-1428 for assistance.
–6–
REV. 0