DAC8512
PIN CONFIGURATIONS
SO-8
V
DD
1
CS 2
CLK 3
8 V
OUT
OPERATION
P-DIP-8 & Cerdip-8
V
DD
CS
CLK
SDI
1
2
3
4
8
V
OUT
GND
CLR
LD
DAC8512
7 GND
TOP VIEW 6 CLR
(Not to Scale)
SDI 4
5 LD
DAC8512
TOP VIEW
(Not to Scale)
7
6
5
PIN DESCRIPTIONS
Pin
1
2
3
4
The DAC8512 is a complete ready to use 12-bit digital-to-analog
converter. It contains a voltage-switched, 12-bit, laser-trimmed
DAC, a curvature-corrected bandgap reference, a rail-to-rail
output op amp, a DAC register, and a serial data input register.
The serial data interface consists of a CLK, serial data in (SDI),
and a load strobe (LD). This basic 3-wire interface offers maxi-
mum flexibility for interface to the widest variety of serial data
input loading requirements. In addition a
CS
select is provided
for multiple packaging loading and a power on reset
CLR
pin to
simplify start or periodic resets.
D/A CONVERTER SECTION
Name Description
V
DD
CS
CLK
SDI
Positive Supply. Nominal value +5 V,
±
5%.
Chip Select. Active low input.
Clock input for the internal serial input shift register.
Serial Data Input. Data on this pin is clocked into the
internal serial register on positive clock edges of the
CLK pin. The Most Significant Bit (MSB) is loaded
first.
LD
Active low input which writes the serial register data
into the DAC register. Asynchronous input.
CLR
Active low digital input that clears the DAC register to
zero, setting the DAC to minimum scale. Asynchronous
input.
GND Analog ground for the DAC. This also serves as the
digital logic ground reference voltage.
V
OUT
Voltage output from the DAC. Fixed output voltage
range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed
full-scale voltage independent of time, temperature and
power supply variations.
The DAC is a 12-bit voltage mode device with an output that
swings from GND potential to the 2.5 volt internal bandgap
voltage. It uses a laser trimmed R-2R ladder which is switched
by N channel MOSFETs. The output voltage of the DAC has a
constant resistance independent of digital input code. The DAC
output is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
5
6
7
8
The DAC’s output is buffered by a low power consumption pre-
cision amplifier. This amplifier contains a differential PNP pair
input stage which provides low offset voltage and low noise, as
well as the ability to amplify the zero-scale DAC output volt-
ages. The rail-to-rail amplifier is configured in a gain of 1.6384
(= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output
(1 mV/LSB). See Figure 3 for an equivalent circuit schematic of
the analog section.
BANDGAP
REFERENCE
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
2R
R
BUFFER
R2
2R
2.5V
2R
R
R1
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
V
OUT
DICE CHARACTERISTICS
V
DD
1
V
OUT
8
GND
GND
CLR
SPDT
N-CH FET
SWITCHES
AV = 4.095/2.5
= 1.638V/V
7
7
6
2
2R
2R
CS
Figure 3. Equivalent DAC8512 Schematic of Analog
Portion
CLK
3
4
SDI
5
LD
The op amp has a 16
µs
typical settling time to 0.01%. There
are slight differences in settling time for negative slowing signals
vs. positive. See the oscilloscope photos in the typical perfor-
mances section of this data sheet.
SUBSTRATE IS COMMON WITH V
DD
.
NUMBER OF TRANSISTORS : 642
DIE SIZE: 0.055 inch
×
0.106 inch; 5830 sq mils
REV. A
–5–
AD [ ANALOG DEVICES ]
