DAC08
10.000V
LSB
MSB
B1 B2 B3 B4 B5 B6 B7 B8 10.000k
I
O
14
I
O
2
E
O
E
O
POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
ZERO-SCALE –LSB
NEG. FULL-SCALE +LSB
NEG. FULL-SCALE
B1
1
1
1
1
0
0
0
B2
1
1
0
0
1
0
0
B3
1
1
0
0
1
0
0
B4
1
1
0
0
1
0
0
B5
1
1
0
0
1
0
0
B6
1
1
0
0
1
0
0
B7
1
1
0
0
1
0
0
B8 E
O
1 –9.920
0 –9.840
1 –0.080
0 0.000
1 +0.080
1 +9.920
0 +10.000
E
O
+10.000
+9.920
+0.160
+0.080
0.000
–9.840
–9.920
10.000k
I
REF
(+) = 2.000mA
4
Figure 10. Basic Bipolar Output Operation
LOW T.C.
4.5k
14
I
REF
(+) 2mA
39k
1V
APPROX
5k
15
–V
REF
I
FS
R15
–V
REF
R
REF
R
REF
14
4
V
REF
10V
I
O
I
O
10k
POT
15
2
NOTE
R
REF
SETS I
FS
; R15 IS FOR
BIAS CURRENT CANCELLATION.
Figure 11. Recommended Full-Scale Adjustment Circuit
10k
5.0k
15V
2
10V
6
V
O
5
5.0k
V+
4
*OR
ADR01
+15V –15V
–15V
V–
C
C
V
LC
I
O
2
5.000k
I
O
4
OP711
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
+15V
Figure 12. Basic Negative Reference Operation
REF01*
B1
POS. FULL RANGE
1
1
E
O
ZERO-SCALE
NEG. FULL-SCALE +1 LSB 0
NEG. FULL-SCALE
0
B2
1
0
0
0
B3
1
0
0
0
B4
1
0
0
0
B5
1
0
0
0
B6
1
0
0
0
B7
1
0
0
0
B8 E
O
1 +4.960
0 0.000
1 –4.960
0 –5.000
Figure 13. Offset Binary Operation
R
L
4
2
I
O
I
O
OP711
0 TO +I
FR
I
FR
=
E
O
R
L
4
2
I
O
I
O
R
L
OP711
0 TO –I
FR
I
FR
=
E
O
R
L
255
I
256
REF
255
I
256
REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP AMP TO I
O
(PIN 2); CONNECT I
O
(PIN 4) TO
GROUND.
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NONINVERTING INPUT OF OP AMP TO I
O
(PIN 2); CONNECT I
O
(PIN 4)
TO GROUND.
Figure 14. Positive Low Impedance Output Operation
Figure 15. Negative Low Impedance Output Operation
V
TH
= V
LC
1.4V
15V CMOS
V
TH
= 7.6V
15V
TTL, DTL
V
TH
= 1.4V
9.1k
V
LC
V
LC
1
6.2k
0.1 F
39k
CMOS, HTL, NMOS
ECL
V+
13k
20k
2N3904
“A”
3k
2N3904
TO PIN 1
V
LC
6.2k
“A”
2N3904
2N3904
3k
20k
TO PIN 1
V
LC
R3
400 A
–5.2V
TEMPERATURE COMPENSATING V
LC
CIRCUITS
Figure 16. Interfacing with Various Logic Families
REV. B
–9–
AD [ ANALOG DEVICES ]
