ADV7302A/ADV7303A
CLKIN_A
t
9
CONTROL
I/PS
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
G0
t
10
G1
G2
G3
Gxxx
Gxxx
C7–C0
B0
B1
B2
B3
Bxxx
Bxxx
S7–S0
R0
R1
R2
Rxxx
Rxxx
t
11
CONTROL
O/PS
S_HSYNC,
S_VSYNC
t
12
t
13
t
14
t
9
= CLOCK HIGH TIME,
t
10
= CLOCK LOW TIME,
t
11
= DATA SETUP TIME,
t
12
= DATA HOLD TIME
Figure 4. HD 4:4:4 RGB Input Data Format Timing Diagram, HD RGB Input Enabled (Input
Mode at Subaddress 01h = 001 or 010)
CLKIN_B
t
9
CONTROL
I/PS
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Cb0
Y0
t
10
Cr0
Y1
Crxxx
Yxxx
t
12
t
11
CONTROL
O/PS
t
12
t
11
t
13
S_HSYNC,
S_VSYNC
t
14
t
9
= CLOCK HIGH TIME,
t
10
= CLOCK LOW TIME,
t
11
= DATA SETUP TIME,
t
12
= DATA HOLD TIME
Figure 5. PS 4:2:2 1 8-Bit Interleaved @ 27 MHz, Input Mode: PS Input Only (Input
Mode at Subaddress 01h = 100)
REV. A
–7–