ADV7180
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Video selection
Bit Description
Reserved
7
6
5
4
3
2
1
0
Comments
Notes
0x01
0
0
Set to default
SQPE
0
1
Disable square pixel mode
Enable square pixel mode
Disable VSYNC processor
Enable VSYNC processor
Set to default
ENVSPROC
0
1
Reserved
BETACAM
0
0
1
Standard video input
Betacam input enable
Disable HSYNC processor
Enable HSYNC processor
Set to default
ENHSPLL
0
1
Reserved
1
0x03
Output control
SD_DUP_AV; duplicates
the AV codes from the
luma into the chroma path
0
1
AV codes to suit 8-bit interleaved data
output
AV codes duplicated (for 16-bit interfaces)
Set as default
Reserved
0
OF_SEL[3:0]; allows the
user to choose from a set
of output formats
0
0
0
0
0
0
0
0
1
0
1
0
Reserved
Reserved
16-bit at LLC 4:2:2
Options apply to
64-lead LQFP only
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
8-bit at LLC 4:2:2 ITU-R BT.656
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TOD; three-state output
drivers; this bit allows the
user to three-state the
output drivers; pixel
outputs, HS, VS, FIELD,
and SFL
0
1
Output pins enabled
See also TIM_OE
and TRI_LLC
Drivers three-stated
VBI_EN; allows VBI data
(Line 1 to Line 21) to be
passed through with
only a minimum amount
of filtering performed
0
1
All lines filtered and scaled
Only active video region filtered
0x04
Extended
output control
Range; allows the user
to select the range of
output values; can be
ITU-R BT.656 compliant or
can fill the whole accessible
number range
0
1
16 ≤ Y ≤ 235, 16 ≤ C/P ≤ 240
1 ≤ Y ≤ 254, 1 ≤ C/P ≤ 254
ITU-R BT.656
Extended range
EN_SFL_PIN
0
1
SFL output is disabled
SFL output
enables encoder
and decoder to be
connected directly
SFL information output on the SFL pin
BL_C_VBI; blank chroma
during VBI; if set, it enables
data in the VBI region
to be passed through the
decoder undistorted
0
1
Decode and output color
Blank Cr and Cb
During VBI
TIM_OE; timing signals
output enable
0
1
HS, VS, FIELD three-stated
HS, VS, FIELD forced active
Controlled by TOD
Rev. G | Page 84 of 120
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