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ADV7180KST48Z-RL 参数 Datasheet PDF下载

ADV7180KST48Z-RL图片预览
型号: ADV7180KST48Z-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4A ?过采样SDTV视频解码器 [10-Bit, 4× Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 120 页 / 2118 K
品牌: ADI [ ADI ]
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ADV7180  
Data Sheet  
Register Select (SR7 to SR0)  
REGISTER ACCESS  
These bits are set up to point to the required starting address.  
I2C SEQUENCER  
The MPU can write to or read from all of the ADV7180 registers  
except the subaddress register, which is write only. The subaddress  
register determines which register the next read or write operation  
accesses. All communications with the part through the bus start  
with an access to the subaddress register. A read/write operation is  
then performed from or to the target address, which increments  
to the next address until a stop command on the bus is performed.  
An I2C sequencer is used when a parameter exceeds eight bits  
and is therefore distributed over two or more I2C registers, for  
example, HSB[10:0].  
When such a parameter is changed using two or more I2C write  
operations, the parameter may hold an invalid value for the  
time between the first I2C being completed and the last I2C  
being completed. In other words, the top bits of the parameter  
may hold the new value while the remaining bits of the parameter  
still hold the previous value.  
To avoid this problem, the I2C sequencer holds the updated bits  
of the parameter in local memory, and all bits of the parameter  
are updated together once the last register write operation has  
completed.  
REGISTER PROGRAMMING  
The following sections describe the configuration for each  
register. The communication register is an 8-bit, write-only  
register. After the part is accessed over the bus and a read/write  
operation is selected, the subaddress is set up. The subaddress  
register determines to or from which register the operation  
takes place. Table 105 lists the various operations under the  
control of the subaddress register for the control port.  
SUB_USR_EN, Address 0x0E[5]  
The correct operation of the I2C sequencer relies on the following:  
This bit splits the register map at Register 0x40.  
All I2C registers for the parameter in question must be  
written to in order of ascending addresses. For example, for  
HSB[10:0], write to Address 0x34 first, followed by 0x35,  
and so on.  
USER MAP  
USER SUB MAP  
2
COMMON I C SPACE  
ADDRESS 0x00 0x3F  
No other I2C can take place between the two (or more) I2C  
writes for the sequence. For example, for HSB[10:0], write to  
Address 0x34 first, immediately followed by 0x35, and so on.  
ADDRESS 0x0E BIT 5 = 0b  
ADDRESS 0x0E BIT 5 = 1b  
2
2
I C SPACE  
I C SPACE  
ADDRESS 0x40 0xFF  
ADDRESS 0x40 0x9C  
NORMAL REGISTER SPACE  
INTERRUPT AND VDP REGISTER SPACE  
Figure 53. Register Access—User Map and User Sub Map  
Rev. E | Page 78 of 120  
 
 
 
 
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