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ADV7180KST48Z-RL 参数 Datasheet PDF下载

ADV7180KST48Z-RL图片预览
型号: ADV7180KST48Z-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4A ?过采样SDTV视频解码器 [10-Bit, 4× Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 120 页 / 2118 K
品牌: ADI [ ADI ]
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Data Sheet  
ADV7180  
Table 85. GS/VPS/PDC/UTC Readback Registers1  
Signal Name  
Register Location  
Dec Address (User Sub Map) Hex Address (User Sub Map)  
GS_VPS_PDC_UTC_BYTE_0[7:0]  
GS_VPS_PDC_UTC_BYTE_1[7:0]  
GS_VPS_PDC_UTC_BYTE_2[7:0]  
GS_VPS_PDC_UTC_BYTE_3[7:0]  
VPS_PDC_UTC_BYTE_4[7:0]  
VPS_PDC_UTC_BYTE_5[7:0]  
VPS_PDC_UTC_BYTE_6[7:0]  
VPS_PDC_UTC_BYTE_7[7:0]  
VPS_PDC_UTC_BYTE_8[7:0]  
VPS_PDC_UTC_BYTE_9[7:0]  
VPS_PDC_UTC_BYTE_10[7:0]  
VPS_PDC_UTC_BYTE_11[7:0]  
VPS_PDC_UTC_BYTE_12[7:0]  
VDP_GS_VPS_PDC_UTC_0[7:0] 132  
0x84  
0x85  
0x86  
0x87  
0x88  
0x89  
0x8A  
0x8B  
0x8C  
0x8D  
0x8E  
0x8F  
0x90  
VDP_GS_VPS_PDC_UTC_1[7:0] 133  
VDP_GS_VPS_PDC_UTC_2[7:0] 134  
VDP_GS_VPS_PDC_UTC_3[7:0] 135  
VDP_VPS_PDC_UTC_4[7:0]  
VDP_VPS_PDC_UTC_5[7:0]  
VDP_VPS_PDC_UTC_6[7:0]  
VDP_VPS_PDC_UTC_7[7:0]  
VDP_VPS_PDC_UTC_8[7:0]  
VDP_VPS_PDC_UTC_9[7:0]  
VDP_VPS_PDC_UTC_10[7:0]  
VDP_VPS_PDC_UTC_11[7:0]  
VDP_VPS_PDC_UTC_12[7:0]  
136  
137  
138  
139  
140  
141  
142  
143  
144  
1 The default value does not apply to readback registers.  
VBI System 2  
GDE_SEL_OLD_ADF, Address 0x4C[3], User Sub Map  
The user has an option of using a different VBI data slicer called  
VBI System 2. This data slicer is used to decode Gemstar and  
closed caption VBI signals only.  
The ADV7180 has a new ancillary data output block that  
can be used by the VDP data slicer and the VBI System 2  
data slicer. The new ancillary data formatter is used by setting  
GDE_SEL_OLD_ADF to 0 (default). See Table 74 and Table 75  
for information about how the data is packaged in the ancillary  
data stream when this bit is set low.  
Using this system, the Gemstar data is available only in the  
ancillary data stream. A special mode enables one line of data to  
be read back through I2C.  
To use the old ancillary data formatter (to be backward compatible  
with the ADV7183B), set GDE_SEL_OLD_ADF to 1. The ancillary  
data format in this section refers to the ADV7183B-compatible  
ancillary data formatter.  
Gemstar Data Recovery  
The Gemstar-compatible data recovery block (GSCD) supports  
1× and 2× data transmissions. In addition, it can serve as a closed  
caption decoder. Gemstar-compatible data transmissions can  
occur only in NTSC. Closed caption data can be decoded in  
both PAL and NTSC.  
Setting GDE_SEL_OLD_ADF to 0 (default) enables a new  
ancillary data system for use with the VDP and VBI System 2.  
The block can be configured via I2C as follows:  
Setting GDE_SEL_OLD_ADF to 1 enables the old ancillary  
data system for use with the VBI System 2 only (ADV7183B  
compatible).  
GDECEL[15:0] allows data recovery on selected video lines  
on even fields to be enabled or disabled.  
GDECOL[15:0] enables the data recovery on selected lines  
for odd fields.  
GDECAD[0] configures the way in which data is  
embedded in the video data stream.  
The format of the data packet depends on the following criteria:  
Transmission is 1× or 2×.  
Data is output in 8-bit or 4-bit format (see the description  
of the bit).  
Data is closed caption (CCAP) or Gemstar compatible.  
The recovered data is not available through I2C but is inserted into  
the horizontal blanking period of an ITU-R BT.656-compatible  
data stream. The data format is intended to comply with the  
recommendation by the International Telecommunications  
Union, ITU-R BT.1364. For more information, visit the  
International Telecommunication Union website. See Figure 50.  
Data packets are output if the corresponding enable bit is set  
(see the GDECEL[15:0], Gemstar Decoding Even Lines,  
Address 0x48[7:0], Address 0x49[7:0] and the GDECOL[15:0],  
Gemstar Decoding Odd Lines, Address 0x4A[7:0], Address  
0x4B[7:0] sections), and the decoder detects the presence of data.  
For video lines where no data is decoded, no data packet is output,  
even if the corresponding line enable bit is set.  
Rev. G | Page 67 of 120  
 
 
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