Data Sheet
ADV7180
The sequence for the interrupt-based reading of the VDP I2C
data registers is as follows for the CCAP standard:
VDP_VITC_MSK
to 1 enables the interrupt on the
Setting
VDP_VITC_Q signal.
Interrupt Status Register Details
1. The user unmasks the CCAP interrupt mask bit (Register 0x50,
Bit 0, user sub map = 1). CCAP data occurs on the incoming
video. VDP slices CCAP data and places it into the VDP
readback registers.
2. The VDP CCAP available bit CC_CAP goes high, and the
VDP module signals to the interrupt controller to stimulate
an interrupt request (for CCAP in this case).
3. The user reads the interrupt status bits (user sub map) and
sees that new CCAP data is available (Register 0x4E, Bit 0,
user sub map = 1).
The following read-only bits contain data detection information
from the VDP module since the status bit was last cleared or
unmasked.
VDP_CCAPD_Q, Address 0x4E[0], User Sub Map
When VDP_CCAPD_Q is 0 (default), CCAP data has not been
detected.
When VDP_CCAPD_Q is 1, CCAP data has been detected.
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E[2],
User Sub Map
4. The user writes 1 to the CCAP interrupt clear bit (Register 0x4F,
Bit 0, user sub map = 1) in the interrupt I2C space (this is a
INTRQ
self-clearing bit). This clears the interrupt on the
pin but does not have an effect in the VDP I2C area.
When VDP_CGMS_WSS_CHNGD_Q is 0 (default), CGMS or
WSS data has not been detected.
5. The user reads the CCAP data from the VDP I2C area.
6. The user writes to Bit CC_CLEAR in the
VDP_STATUS_CLEAR register, (Register 0x78, Bit 0,
user sub map = 1) to signify the CCAP data has been read
(therefore the VDP CCAP can be updated at the next
occurrence of CCAP).
When VDP_CGMS_WSS_CHNGD_Q is 1, CGM or WSS data
has been detected.
VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E[4],
User Sub Map
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 0 (default),
Gemstar, PDC, UTC, or VPS data has not been detected.
7. The user goes back to Step 2.
Interrupt Mask Register Details
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 1, Gemstar,
PDC, UTC, or VPS data has been detected.
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
VDP_VITC_Q, Address 0x4E[6], User Sub Map,
Read Only
VDP_CCAPD_MSK
, Address 0x50[0], User Sub Map
When VDP_VITC_Q is 0 (default), VITC data has not been
detected.
VDP_CCAPD_MSK
on the VDP_CCAPD_Q signal.
Setting
to 0 (default) disables the interrupt
When VDP_VITC_Q is 1, VITC data has been detected.
VDP_CCAPD_MSK
Setting
VDP_CCAPD_Q signal.
to 1 enables the interrupt on the
Interrupt Status Clear Register Details
It is not necessary to write 0 to these write-only bits because
they automatically reset after they have been set to 1 (self-clearing).
VDP_CGMS_WSS_CHNGD_MSK
Sub Map
, Address 0x50[2], User
VDP_CCAPD_CLR, Address 0x4F[0], User Sub Map
VDP_CGMS_WSS_CHNGD_MSK
Setting
the interrupt on the VDP_CGMS_WSS_ CHNGD_Q signal.
VDP_CGMS_WSS_CHNGD_MSK
to 0 (default) disables
Setting VDP_CCAPD_CLR to 1 clears the VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F[2],
User Sub Map
Setting
to 1 enables the
interrupt on the VDP_CGMS_WSS_CHNGD_Q signal.
Setting VDP_CGMS_WSS_CHNGD_CLR to 1 clears the
VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_MSK
Address 0x50[4], User Sub Map
,
VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F[4], User Sub Map
VDP_GS_VPS_PDC_UTC_CHNG_MSK
(default) disables the interrupt on the
Setting
to 0
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
Setting VDP_GS_VPS_PDC_UTC_CHNG_CLR to 1 clears the
VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_MSK
Setting
to 1 enables
the interrupt on the VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
VDP_VITC_CLR, Address 0x4F[6], User Sub Map
VDP_VITC_MSK
, Address 0x50[6], User Sub Map
Setting VDP_VITC_CLR to 1 clears the VDP_VITC_Q bit.
VDP_VITC_MSK
Setting
to 0 (default) disables the interrupt
on the VDP_VITC_Q signal.
Rev. G | Page 61 of 120
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