Data Sheet
ADV7180
ANALOG_INPUT_1
Y
THE SUGGESTED INPUT ARRANGEMENT
IS AS SEEN ON THE EVAL BOARD AND IS
DIRECTLY SUPPORTED BY INSEL.
0.1µF
A
A
A
A
A
A
1
2
3
4
5
6
IN
IN
IN
IN
IN
IN
36Ω
39Ω
D
_1.8V
D
_1.8V
VDD
VDD
ANALOG_INPUT_2
CVBS
0.1µF
0.1µF
10nF
0.1µF
10nF
36Ω
39Ω
D
_3.3V
0.1µF
A
_1.8V
VDDIO
VDD
ANALOG_INPUT_3
YC_Y
0.1µF
0.1µF
10nF
D
_3.3V
36Ω
P
_1.8V
VDD
VDDIO
39Ω
10nF
ANALOG_INPUT_4
Cr
10nF
0.1µF
0.1µF
10nF
0.1µF
36Ω
P[0:7]
39Ω
ANALOG_INPUT_5
Cb
0.1µF
26
27
33
34
35
36
A
A
A
A
A
A
1
2
3
4
5
6
A
1
2
3
4
5
6
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
22
20
12
11
10
9
P0
P1
P2
P3
P4
P5
P6
P7
P0
P1
P2
P3
P4
P5
P6
P7
36Ω
A
A
A
A
A
39Ω
ANALOG_INPUT_6
YC_C
0.1µF
8
7
36Ω
39Ω
ADV7180WBST48Z
LQFP–48
KEEP VREFN AND VREFP CAPACITOR AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME
SIDE OF THE PCB AS THE ADV7180.
30
29
VREFN
VREFP
0.1µF
46
INTRQ
INT
41
42
6
GPO3
GPO2
GPO1
GPO0
GPO3
GPO2
GPO1
GPO0
5
17
16
XTAL
45
47pF
VS/FIELD
VS/FIELD
*
28.63636MHz
1MΩ
47
3
HS
HS
XTAL1
47pF
SFL
SFL
P
_1.8V
VDD
37
21
EXTERNAL
RESET
RESET
NC
15, 48
24
LOOP FILTER
PWRDWN
POWER_DOWN
10nF
ELPF
D
_3.3V
VDDIO
82nF
4kΩ
38
1.69kΩ
ALSB
2
TIE HI: I C ADDRESS = 42
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
2
TIE LOW: I C ADDRESS = 40
14
LLC
LLC
33Ω
40
39
SCLK
SCLK
SDA
SDATA
33Ω
NOTES
1. NC = NO CONNECT.
*REFER TO ANALOG DEVICES CRYSTAL APPLICATION NOTE FOR PROPER CAPACITOR LOADING
Figure 57. 48-Lead LQFP Typical Connection Diagram
Rev. G | Page 113 of 120
ADI [ ADI ]
