ADV7180
Data Sheet
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 5.
Parameter
Symbol Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
28.6363
MHz
ppm
50
I2C PORT
SCLK Frequency
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Times
SCLK and SDA Fall Times
Setup Time for Stop Condition
RESET FEATURE
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
t9:t10
45:55
55:45 % duty cycle
t11
t12
Negative clock edge to start of valid data
(tACCESS = t10 − t11)
End of valid data to negative clock edge
(tHOLD = t9 + t12)
3.6
2.4
ns
ns
Data Output Transitional Time
Timing Diagrams
t5
t3
t3
SDATA
SCLK
t1
t6
t4
t7
t8
t2
Figure 6. I2C Timing
t9
t10
OUTPUT LLC
t11
t12
OUTPUTS P0 TO P15, VS,
HS, FIELD,
SFL
Figure 7. Pixel Port and Control Output Timing
Rev. G | Page 10 of 120
ADI [ ADI ]
