ADV7172/ADV7173
t
5
t
3
SDATA
t
3
t
6
t
1
SCLOCK
t
2
t
7
t
4
t
8
Figure 1. MPU Port Timing Diagram
CLOCK
t
9
CONTROL
I/PS
HSYNC,
FIELD/VSYNC,
BLANK
t
10
t
12
PIXEL INPUT
DATA
HSYNC,
FIELD/VSYNC,
BLANK,
CSO_HSO,
VSO,
CLAMP
Cb
Y
Cr
Y
Cb
Y
t
11
t
13
CONTROL
O/PS
t
14
Figure 2. Pixel and Control Data Timing Diagram
TXTREQ
t
16
CLOCK
t
17
TXT
t
18
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
3 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 3. Teletext Timing Diagram
DAC Average Current Consumption
DAC D, E, F: The average current consumed by each DAC is the DAC output current as determined by R
SET2
/V
REF
(see Appendix 8).
DAC A, B, C: In
normal power mode
the average current consumed by each DAC is the DAC output current as determined by R
SET1
(see Appendix 8).
In
Low Power Mode
the average current consumed by each DAC is approximately half the DAC output current as determined by R
SET1.
Table I. Allowable Operating Configurations
DACs
A, B, C
3 DACs ON
3 DACs ON
3 DACs ON
3 DACs ON
3 DACs ON
Output
Current
37 mA
37 mA
37 mA
8.66 mA
4.33 mA
Average
DAC Current
Consumption
See Above
18.5 mA (See Above)
18.5 mA (See Above)
See Above
See Above
DACs
D, E, F
3 DACs ON
3 DACs ON
3 DACs OFF
3 DACs ON
3 DACs ON
Output
Current
8.66 mA
8.66 mA
8.66 mA
4.33 mA
Average
DAC Current
Consumption
See Above
See Above
See Above
See Above
See Above
Power
Mode
Normal
Low Power
Low Power
Normal
Normal
5 V?
No
No
Yes
Yes
Yes
3 V?
Yes
Yes
Yes
Yes
Yes
–8–
REV. A
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