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ADV7128KR30 参数 Datasheet PDF下载

ADV7128KR30图片预览
型号: ADV7128KR30
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 80兆赫, 10位视频DAC [CMOS 80 MHz, 10-Bit Video DAC]
分类和应用:
文件页数/大小: 8 页 / 138 K
品牌: AD [ ANALOG DEVICES ]
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ADV7128
TERMINOLOGY
Color Video (RGB)
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Gray Scale
The maximum positive polarity amplitude of the video signal.
Video Signal
The discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
Raster Scan
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
The most basic method of sweeping a CRT one line at a time to
generate and display images.
If we, therefore, have a graphics system with a 1024
×
1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate = 1024
×
1024
×
60/0.8
= 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7128
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV7128 be driven by a TTL buffer (e.g.,
74F244).
I
OUT
DATA
CIRCUIT DESCRIPTION AND OPERATION
The ADV7128 contains one 10-bit D/A converter, with one in-
put channel containing a 10-bit register. Also integrated on
board the part is a reference amplifier.
Digital Inputs
Ten bits of data (color information) D0–D9 are latched into the
device on the rising edge of each clock cycle. This data is pre-
sented to the 10-bit DAC and is then converted to an analog
output waveform. See Figure 2.
CLOCK
DIGITAL
INPUTS
D0–D9
mA
17.61
V
0.66
WHITE
LEVEL
ANALOG
OUTPUTS
I
OUT
100
IRE
Figure 2. Video Data Input/Output
0
NOTES
0
BLACK
LEVEL
All these digital inputs are specified to accept TTL logic levels.
Clock Input
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
The CLOCK input of the ADV7128 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following
equation:
Dot Rate = (Horiz Res)
×
(Vert Res)
×
(Refresh Rate)/
(Retrace Factor)
Horiz Res
Vert Res
Refresh Rate
=
=
=
Number of Pixels/Line.
Number of Lines/Frame.
Horizontal Scan Rate. This is the rate at
which the screen must be refreshed, typi-
cally 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
Total Blank Time Factor. This takes into
account that the display is blanked for a
certain fraction of the total duration of
each frame (e.g., 0.8).
2. V
REF
= 1.235V, R
SET
= 560Ω.
3. RS–343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. I
OUT
Video Output Waveform
Table I. Video Output Truth Table for the ADV7128
Description
WHITE LEVEL
VIDEO
VIDEO to BLACK
BLACK LEVEL
I
OUT1
17.62
video
video
0
DAC Input Data
3FF
data
data
00H
NOTE
1
Typical with full scale = 17.62 mA. V
REF
= 1.235 V, R
SET
= 560
Ω.
Retrace Factor =
REV. 0
–5–