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ADV7125 参数 Datasheet PDF下载

ADV7125图片预览
型号: ADV7125
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz三通道,8位高速视频DAC [CMOS, 330 MHz Triple 8-Bit High Speed Video DAC]
分类和应用:
文件页数/大小: 12 页 / 254 K
品牌: ADI [ ADI ]
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ADV7125–SPECIFICATIONS  
(VAA = 5 V 5%, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications TMIN to  
5 V ELECTRICAL CHARACTERISTICS TMAX1, unless otherwise noted, TJ MAX = 110؇C.)  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions1  
STATIC PERFORMANCE  
Resolution (Each DAC)  
Integral Nonlinearity (BSL)  
Differential Nonlinearity  
8
–1  
–1  
Bits  
LSB  
LSB  
0.4  
0.25  
+1  
+1  
Guaranteed Monotonic  
VIN = 0.0 V or VDD  
DIGITAL AND CONTROL INPUTS  
Input High Voltage, VIH  
Input Low Voltage, VIL  
Input Current, IIN  
PSAVE Pull-Up Current  
Input Capacitance, CIN  
2
V
V
µA  
µA  
pF  
0.8  
+1  
–1  
20  
10  
ANALOG OUTPUTS  
Output Current  
Output Current  
2.0  
2.0  
26.5  
18.5  
5
mA  
mA  
%
V
kΩ  
pF  
Green DAC, Sync = High  
R/G/B DAC, Sync = Low  
DAC-to-DAC Matching  
Output Compliance Range, VOC  
Output Impedance, ROUT  
Output Capacitance, COUT  
Offset Error  
1.0  
0
1.4  
100  
10  
IOUT = 0 mA  
Tested with DAC Output = 0 V  
FSR = 18.62 mA  
–0.025  
–5.0  
+0.025  
+5.0  
% FSR  
% FSR  
Gain Error2  
VOLTAGE REFERENCE (Ext. and Int.)  
Reference Range, VREF  
1.12  
1.235  
1.35  
V
POWER DISSIPATION  
Digital Supply Current3  
Digital Supply Current3  
Digital Supply Current3  
Analog Supply Current  
Analog Supply Current  
Standby Supply Current4  
3.4  
10.5  
18  
67  
8
9
mA  
mA  
mA  
mA  
mA  
mA  
fCLK = 50 MHz  
fCLK = 140 MHz  
fCLK = 240 MHz  
RSET = 530 Ω  
RSET = 4933 Ω  
15  
25  
72  
2.1  
5.0  
0.5  
PSAVE = Low, Digital, and Control  
Inputs at VDD  
Power Supply Rejection Ratio  
0.1  
%/%  
NOTES  
1Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.  
2Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF/RSET × K × (FFH) × 4 and K = 7.9896.  
3Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD  
4These max/min specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.  
.
Specifications subject to change without notice.  
–2–  
REV. 0  
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