ADV7125
Analog Signal Interconnect
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly termi-
nated 75 Ω configuration). This termination resistance should
be as close as possible to the ADV7125 to minimize reflections.
The ADV7125 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
Additional information on PCB design is available in an application
note entitled Design and Layout of a Video Graphics System for
Reduced EMI. This application note is available from Analog
Devices, publication no. E1309–15–10/89 (www.analog.com/
library/applicationNotes/designTech/AN333.pdf).
POWER SUPPLY DECOUPLING (0.1F AND 0.01F
CAPACITOR FOR EACH V GROUP)
AA
L1
0.1F
0.01F
13, 29,
30
(FERRITE BEAD)
V
V
0.1F
AA
CC
V
AA
5V (V
)
COMP
R7–R0
AA
ANALOG GROUND PLANE
0.1F
10F
33F
41–48
5V (V
)
V
AA
REF
R
SET
3–10
R
SET
530⍀
MONITOR
(CRT)
VIDEO
COAXIAL CABLE
G7–G0
B7–B0
DATA
75⍀
INPUTS
IOR
IOG
IOB
16–23
75⍀
75⍀
75⍀
75⍀
75⍀ 75⍀
ADV7125
BNC
CONNECTORS
SYNC
IOR
BLANK
COMPLEMENTARY
OUTPUTS
IOG
IOB
CLOCK
PSAVE
GND
1, 2, 14, 15,
25, 26, 39, 40
Figure 7. Typical Connection Diagram
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7؇
3.5؇
0؇
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
–12–
REV. 0
ADI [ ADI ]
