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ADV7125KST140 参数 Datasheet PDF下载

ADV7125KST140图片预览
型号: ADV7125KST140
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz三通道,8位高速视频DAC [CMOS, 330 MHz Triple 8-Bit High Speed Video DAC]
分类和应用: 转换器数模转换器
文件页数/大小: 12 页 / 254 K
品牌: AD [ ANALOG DEVICES ]
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ADV7125
3.3 V TIMING SPECIFICATIONS
Parameter
ANALOG OUTPUTS
Analog Output Delay, t
6
Analog Output Rise/Fall Time, t
74
Analog Output Transition Time, t
85
Analog Output Skew, t
96
CLOCK CONTROL
f
CLK7
f
CLK7
f
CLK7
f
CLK7
Data and Control Setup, t
16
Data and Control Hold, t
26
Clock Period, t
3
Clock Pulsewidth High, t
46
Clock Pulsewidth Low, t
56
Clock Pulsewidth High, t
46
Clock Pulsewidth Low, t
56
Clock Pulsewidth High, t
46
Clock Pulsewidth Low, t
56
Clock Pulsewidth High, t
4
Clock Pulsewidth Low, t
5
Pipeline Delay, t
PD6
PSAVE Up Time, t
106
2
3.0
1
(V
AA
=
3
V to 3.6 V , V
REF
= 1.235 V, R
SET
= 560 , C
L
= 10 pF. All specifications T
MIN
to T
MAX
, unless otherwise noted, T
J MAX
= 110 C.)
Typ
7.5
1.0
15
1
Max
Unit
ns
ns
ns
ns
Min
Condition
2
50
140
240
330
0.2
1.5
3
1.4
1.4
1.875
1.875
2.85
2.85
8.0
8.0
1.0
1.0
4
1.0
10
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
330 MHz Grade
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 50 MHz
f
CLK_MAX
= 50 MHz
NOTES
1
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) for 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T
MIN
to T
MAX
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
t
3
t
4
CLOCK
DIGITAL INPUTS
(R7–R0, G7–G0, B7–B0,
SYNC, BLANK)
t
5
t
2
DATA
t
1
t
6
t
8
ANALOG OUTPUTS
(IOR,
IOR,
IOG,
IOG,
IOB,
IOB)
t
7
NOTES
1. OUTPUT DELAY (
t
6
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t
7
) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (
t
8
) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
Figure 1. Timing Diagram
REV. 0
–5–