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ADV7125KST50 参数 Datasheet PDF下载

ADV7125KST50图片预览
型号: ADV7125KST50
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz三通道,8位高速视频DAC [CMOS, 330 MHz Triple 8-Bit High Speed Video DAC]
分类和应用:
文件页数/大小: 12 页 / 254 K
品牌: AD [ ANALOG DEVICES ]
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ADV7125
3.3 V ELECTRICAL CHARACTERISTICS
1
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current, I
IN
PSAVE Pull-Up Current
Input Capacitance, C
IN
ANALOG OUTPUTS
Output Current
Output Current
DAC-to-DAC Matching
Output Compliance Range, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
Offset Error
Gain Error
3
VOLTAGE REFERENCE (Ext.)
Reference Range, V
REF
VOLTAGE REFERENCE (Int.)
Reference Range, V
REF
POWER DISSIPATION
Digital Supply Current
4
Digital Supply Current
4
Digital Supply Current
4
Digital Supply Current
4
Analog Supply Current
Analog Supply Current
Standby Supply Current
Power Supply Rejection Ratio
Min
(V
AA
= 3.0 V to 3.6 V, V
REF
= 1.235 V, R
SET
= 560 , C
L
= 10 pF. All specifications
T
MIN
to T
MAX2
, unless otherwise noted, T
J MAX
= 110 C.)
Typ
Max
8
+1
+1
Unit
Bits
LSB
LSB
V
V
µA
µA
pF
mA
mA
%
V
kΩ
pF
% FSR
% FSR
V
V
5.0
12.0
15
72
5.0
0.5
mA
mA
mA
mA
mA
mA
mA
%/%
f
CLK
= 50 MHz
f
CLK
= 140 MHz
f
CLK
= 240 MHz
f
CLK
= 330 MHz
R
SET
= 560
R
SET
= 4933
PSAVE = Low, Digital, and Control
Inputs at V
DD
Test Conditions
2
R
SET
= 680
R
SET
= 680
R
SET
= 680
–1
–1
2.0
±
0.5
±
0.25
0.8
–1
20
10
2.0
2.0
1.0
0
70
10
0
0
1.12
1.235
1.235
2.2
6.5
11
16
67
8
2.1
0.1
1.4
26.5
18.5
+1
V
IN
= 0.0 V or V
DD
Green DAC, Sync = High
R/G/B DAC, Sync = Low
0
Tested with DAC Output = 0 V
FSR = 18.62 mA
1.35
NOTES
1
These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
2
Temperature range T
MIN
to T
MAX
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3
Gain error = (Measured (FSC)/Ideal (FSC) –1)
×
100), where Ideal = V
REF
/R
SET
×
K
×
(FFH)
×
4 and K = 7.9896.
4
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V
DD
.
Specifications subject to change without notice.
REV. 0
–3–