ADuM2400/ADuM2401/ADuM2402
Parameter
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM2402 Total Supply Current, Four Channels
DC to 2 Mbps
V
DD1
Supply Current
5 V/3 V Operation
3 V/5 V Operation
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRWZ and CRWZ Grades Only)
V
DD1
Supply Current
5 V/3 V Operation
3 V/5 V Operation
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
90 Mbps (CRWZ Grade Only)
V
DD1
Supply Current
5 V/3 V Operation
3 V/5 V Operation
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Symbol
I
DD2 (90)
Min
Typ
18
31
Max Unit
27
43
mA
mA
Data Sheet
Test Conditions
45 MHz logic signal frequency
45 MHz logic signal frequency
I
DD1 (Q)
1.5
0.9
I
DD2 (Q)
0.9
1.5
I
DD1 (10)
5.6
3.0
I
DD2 (10)
3.0
5.6
I
DD1 (90)
44
24
I
DD2 (90)
24
44
I
IA
, I
IB
, I
IC
,
I
ID
, I
E1
, I
E2
V
IH
, V
EH
−10
+0.01
39
62
+10
mA
mA
μA
45 MHz logic signal frequency
45 MHz logic signal frequency
0 V ≤ V
IA
, V
IB
, V
IC
, V
ID
≤ V
DD1
or V
DD2
,
0 V ≤ V
E1
, V
E2
≤ V
DD1
or V
DD2
62
39
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
4.2
7.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
7.0
4.2
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
1.5
2.1
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
2.1
1.5
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
2.0
1.6
V
IL
, V
EL
0.8
0.4
V
OAH
, V
OBH
, (V
DD1
or V
DD2
) −
V
OCH
, V
ODH
0.1
(V
DD1
or V
DD2
) −
0.4
V
OAL,
V
OBL
,
V
OCL
, V
ODL
(V
DD1
or V
DD2
)
(V
DD1
or V
DD2
) −
0.2
0.0
0.1
0.04
0.1
0.2
0.4
V
V
V
V
V
V
V
V
V
I
Ox
= −20 μA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 μA, V
Ix
= V
IxL
I
Ox
= 400 μA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM240xARWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
− t
PHL
Propagation Delay Skew
Channel-to-Channel Matching
ADuM240xBRWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/
t
PSKOD
PW
t
PHL
, t
PLH
10
15
35
1
50
70
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
100
50
ns
Mbps
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Rev. E | Page 8 of 24
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