ADuM1410/ADuM1411/ADuM1412
Parameter
3 V/5 V Operation
ADuM1412, Total Supply Current, Four
Channels
DC to 2 Mbps
V
DD1
Supply Current
5 V/3 V Operation
3 V/5 V Operation
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRWZ Version Only)
V
DD1
Supply Current
5 V/3 V Operation
3 V/5 V Operation
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
All Models
Input Currents
I
DD2 (Q)
1.0
2.0
1.8
2.6
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
Symbol
Min
Typ
3.8
Max Unit
5.3
mA
Test Conditions
5 MHz logic signal frequency
I
DD1 (Q)
2.0
1.0
2.6
1.8
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
I
DD1 (10)
4.6
2.6
I
DD2 (10)
2.6
4.6
I
IA
, I
IB
, I
IC
, I
ID
, −10
I
CTRL1
, I
CTRL2
,
I
DISABLE
V
IH
2.0
1.6
V
IL
+0.01
3.8
6.5
+10
mA
mA
μA
5 MHz logic signal frequency
5 MHz logic signal frequency
0 V ≤ V
IA
,V
IB
, V
IC
,V
ID
≤ V
DD1
or V
DD2
,
0 V ≤ V
CTRL1
,V
CTRL2
≤ V
DD1
or V
DD2
,
0 V ≤ V
DISABLE
≤ V
DD1
6.5
3.8
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Logic Low Output Voltages
V
V
0.8
0.4
V
V
V
V
V
V
V
V
OAH
, V
OBH
,
V
OCH
, V
ODH
V
OAL
, V
OBL
,
V
OCL
, V
ODL
(V
DD1
or V
DD2
) − 0.1
(V
DD1
or V
DD2
) − 0.4
(V
DD1
or V
DD2)
(V
DD1
or V
DD2
) − 0.2
0.0
0.04
0.2
0.1
0.1
0.4
I
Ox
= −20 μA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 μA, V
Ix
= V
IxL
I
Ox
= 400 μA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM141xARWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
Propagation Delay Skew
Channel-to-Channel Matching
ADuM141xBRWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
Rev. G | Page 8 of 24
1
25
70
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
100
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
10
25
35
5
60
5
30
5
6
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