ADuM1410/ADuM1411/ADuM1412
APPLICATION INFORMATION
PC BOARD LAYOUT
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
The ADuM141x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
(see Figure 16). Bypass capacitors are most conveniently con-
nected between Pin 1 and Pin 2 for VDD1, and between Pin 15
and Pin 16 for VDD2. The capacitor value should be between
0.01 μF and 0.1 μF. The total lead length between both ends of
the capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should also be considered unless the ground pair on
each package side is connected close to the package.
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 2 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than approximately 5 μs, the
input side is assumed to be unpowered or nonfunctional, in
which case the isolator output is forced to a default state (see
Table 10) by the watchdog timer circuit.
V
GND
V
DD1
DD2
GND
The magnetic field immunity of the ADuM141x is determined
by the changing magnetic field which induces a voltage in the
transformer’s receiving coil large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM141x is examined because it represents the most suscep-
tible mode of operation.
1
IA
IB
IC
ID
2
V
V
V
V
V
V
V
V
OA
OB
OC
OD
DISABLE
GND
CTRL
GND
1
2
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it
is important to minimize board coupling across the isolation
barrier. Furthermore, design the board layout such that any
coupling that does occur equally affects all pins on a given
component side. Failure to ensure this can cause voltage
differentials between pins exceeding the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
2
V = (−dβ/dt)∑ π rn ; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input to
output propagation delay time for a high to low transition may
differ from the propagation delay time of a low to high
transition.
Given the geometry of the receiving coil in the ADuM141x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field at a given frequency can be calculated. The result
is shown in Figure 18.
INPUT (V
)
50%
IX
100
tPLH
tPHL
OUTPUT (V
)
50%
OX
10
Figure 17. Propagation Delay Parameters
1
Pulse width distortion is the maximum difference between
these two propagation delay values, and it is an indication of
how accurately the timing of the input signal is preserved.
0.1
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM141x component.
0.01
0.001
1k
10k
100k
1M
10M
100M
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM141x
components operating under the same conditions.
MAGNETIC FIELD FREQUENCY (Hz)
Figure 18. Maximum Allowable External Magnetic Flux Density
Rev. E | Page 18 of 20
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