ADuM1300/ADuM1301
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
Data Sheet
All voltages are relative to their respective ground. 4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V. These
specifications do not apply to
and
automotive grade versions.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
Total Supply Current, Three Channels
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
90 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
Total Supply Current, Three Channels
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
90 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Symbol
I
DDI (Q)
I
DDO (Q)
Min
Typ
0.50
0.19
Max Unit
0.53
0.24
mA
mA
Test Conditions
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
I
DD1 (90)
I
DD2 (90)
1.6
0.7
6.5
1.9
57
16
2.5
1.0
8.1
2.5
77
18
mA
mA
mA
mA
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
45 MHz logic signal freq.
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
I
DD1 (90)
I
DD2 (90)
I
IA
, I
IB
, I
IC
, I
E1
, I
E2
V
IH
, V
EH
V
IL
, V
EL
V
OAH
, V
OBH
, V
OCH
V
OAL
, V
OBL
, V
OCL
−10
2.0
1.3
1.0
5.0
3.4
43
29
2.1
1.4
6.2
4.2
57
37
mA
mA
mA
mA
mA
mA
µA
V
V
V
V
V
V
V
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
45 MHz logic signal freq.
0 V ≤ V
IA
, V
IB
, V
IC
≤ V
DD1
or V
DD2
,
0 V ≤ V
E1
, V
E2
≤ V
DD1
or V
DD2
+0.01 +10
0.8
(V
DD1
or V
DD2
) − 0.1
(V
DD1
or V
DD2
) − 0.4
5.0
4.8
0.0
0.04
0.2
0.1
0.1
0.4
I
Ox
= −20 µA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxL
I
Ox
= 400 µA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
/t
PSKOD
1
50
65
11
1000 ns
Mbps
100 ns
40
ns
ps/°C
50
ns
50
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Rev. K | Page 4 of 32
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