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ADUM1201ARZ-RL7 参数 Datasheet PDF下载

ADUM1201ARZ-RL7图片预览
型号: ADUM1201ARZ-RL7
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道数字隔离器 [Dual-Channel Digital Isolators]
分类和应用: 接口集成电路光电二极管PC
文件页数/大小: 20 页 / 1156 K
品牌: AD [ ANALOG DEVICES ]
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ADuM1200/ADuM1201
1000
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 1m
100
POWER CONSUMPTION
The supply current at a given channel of the ADuM120x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
For each input channel, the supply current is given by
I
DDI
= I
DDI
(Q)
I
DDI
= I
DDI
(D)
× (2f
– f
r
) +
I
DDI (Q)
f
≤ 0.5f
r
f > 0.5f
r
for each output channel, the supply current is given by
04642-0-014
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
I
DDO
= I
DDO
(Q)
f
≤ 0.5f
r
Figure 14. Maximum Allowable Current for Various
Current-to-ADuM120x Spacings
I
DDO
= (I
DDO
(D)
+ (0.5 × 10
−3
) ×
C
L
V
DDO
) × (2f
– f
r
) +
I
DDO
(Q)
f
> 0.5f
r
where:
I
DDI (D)
,
I
DDO (D)
are the input and output dynamic supply currents
per channel (mA/Mbps).
C
L
is the output load capacitance (pF).
V
DDO
is the output supply voltage (V).
f
is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
f
r
is the input stage refresh rate (Mbps).
I
DDI (Q)
,
I
DDO (Q)
are the specified input and output quiescent
supply currents (mA).
To calculate the total I
DD1
and I
DD2
supply current, the supply
currents for each input and output channel corresponding to
I
DD1
and I
DD2
are calculated and totaled. Figure 6 and Figure 7
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 8 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 9 through Figure 11 provide total I
DD1
and I
DD2
supply current as a function of data rate for
ADuM1200 and ADuM1201 channel configurations.
Note that at combinations of strong magnetic fields and high
frequencies, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
threshold of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
Rev. B | Page 16 of 20