Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
TIMING SPECIFICATIONS
Table 2. External Memory Write Cycle
Parameter
CLK1
Min
Typ
Max
Unit
UCLK
tMS_AFTER_CLKH
tADDR_AFTER_CLKH
tAE_H_AFTER_MS
tAE
tHOLD_ADDR_AFTER_AE_L
tHOLD_ADDR_BEFORE_WR_L
tWR_L_AFTER_AE_L
tDATA_AFTER_WR_L
tWR
tWR_H_AFTER_CLKH
tHOLD_DATA_AFTER_WR_H
tBEN_AFTER_AE_L
tRELEASE_MS_AFTER_WR_H
0
4
4
8
ns
ns
½ CLK
(XMxPAR[14:12] + 1) × CLK
½ CLK + (!XMxPAR[10]) × CLK
(!XMxPAR[8]) × CLK
½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK
8
0
12
4
ns
ns
(XMxPAR[7:4] + 1) × CLK
(!XMxPAR[8]) × CLK
½ CLK
(!XMxPAR[8] + 1) × CLK
1 See Table 78.
CLK
CLK
tMS_AFTER_CLKH
MSx
AE
tWR_L_AFTER_AE_L
tAE_H_AFTER_MS
tWR
tRELEASE_MS_AFTER_WR_H
tAE
tWR_H_AFTER_CLKH
WS
RS
tHOLD_DATA_AFTER_WR_H
tHOLD_ADDR_AFTER_AE_L
tHOLD_ADDR_BEFORE_WR_L
tADDR_AFTER_CLKH
9ABC
tDATA_AFTER_WR_L
AD[16:1]
FFFF
5678
9ABE
1234
tBEN_AFTER_AE_L
BLE
BHE
A16
Figure 12. External Memory Write Cycle (See Table 78)
Rev. F | Page 13 of 104
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