欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADSP-BF532SBST400 参数 Datasheet PDF下载

ADSP-BF532SBST400图片预览
型号: ADSP-BF532SBST400
PDF下载: 下载PDF文件 查看货源
内容描述: Blackfin嵌入式处理器 [Blackfin Embedded Processor]
分类和应用: 外围集成电路时钟
文件页数/大小: 56 页 / 672 K
品牌: AD [ ANALOG DEVICES ]
 浏览型号ADSP-BF532SBST400的Datasheet PDF文件第2页浏览型号ADSP-BF532SBST400的Datasheet PDF文件第3页浏览型号ADSP-BF532SBST400的Datasheet PDF文件第4页浏览型号ADSP-BF532SBST400的Datasheet PDF文件第5页浏览型号ADSP-BF532SBST400的Datasheet PDF文件第6页浏览型号ADSP-BF532SBST400的Datasheet PDF文件第7页浏览型号ADSP-BF532SBST400的Datasheet PDF文件第8页浏览型号ADSP-BF532SBST400的Datasheet PDF文件第9页  
a
FEATURES
Blackfin®
Embedded Processor
ADSP-BF531/ADSP-BF532/ADSP-BF533
External Memory Controller with glueless support for
SDRAM, SRAM, FLASH, and ROM
Flexible memory booting options from SPI and external
memory
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit Shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core V
DD
with on-chip voltage regulation
3.3 V and 2.5 V tolerant I/O
160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead
LQFP packages
PERIPHERALS
Parallel Peripheral Interface (PPI)/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, sup-
porting eight stereo I
2
S channels
12-channel DMA controller
SPI compatible port
Three Timer/Counters with PWM support
UART with support for IrDA®
Event Handler
Real-Time Clock
Watchdog Timer
Debug/JTAG interface
On-chip PLL capable of 1x to 63x frequency multiplication
Core Timer
MEMORY
Up to 148K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
64K bytes of instruction SRAM
32K bytes of data SRAM/Cache
32K bytes of data SRAM
4K bytes of scratchpad SRAM
Two dual-channel memory DMA controllers
Memory Management Unit providing memory protection
JTAG TEST AND
EMULATION
EVENT
CONTROLLER/
CORE TIMER
WATCHDOG TIMER
VOLTAGE
REGULATOR
B
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
CORE / SYSTEM BUS INTERFACE
REAL-TIME CLOCK
UART PORT
IRDA®
TIMER0, TIMER1,
TIMER2
PPI / GPIO
DMA
CONTROLLER
SERIAL PORTS (2)
SPI PORT
BOOT ROM
EXTERNAL PORT
FLASH, SDRAM
CONTROL
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.