ADSP-BF531/ADSP-BF532/ADSP-BF533
ADDRE SS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
P1
P0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG0
DAG 1
S EQUENCER
ALIG N
DECO DE
LD0 32 BITS
R7
R6
R5
R4
R3
R2
R1
R0
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
BARREL
SHIFTER
40
40
16
8
8
8
16
8
CONTRO L
UNIT
LOO P BUF FE R
LD1 32 BITS
SD 32 BI TS
A0
A1
DATA ARITHME TIC UNI T
Figure 2. Blackfin Processor Core
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
RESERVED
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (64K BYTE)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTE)
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTE)
0xFF80 4000
DATA BANK A SRAM (16K BYTE)
0xFF80 0000
RESERVED
0xEF00 0000
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
EXTERNAL MEMORY MAP
INTERNAL MEMORY MAP
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
RESERVED
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTE)
0xFF90 4000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTE)
0xFF80 4000
RESERVED
0xEF00 0000
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
EXTERNAL MEMORY MAP
INTERNAL MEMORY MAP
0xFFB0 0000
0xFFB0 0000
RESERVED
RESERVED
Figure 3. ADSP-BF533 Internal/External Memory Map
Figure 4. ADSP-BF532 Internal/External Memory Map
Rev. 0 |
Page 5 of 56 | March 2004