ADSP-BF531/ADSP-BF532/ADSP-BF533
as the RTC, may still be running but will not be able to access
internal resources or external memory. This powered-down
mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in Deep Sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the Active mode.
Assertion of RESET while in Deep Sleep mode causes the pro-
cessor to transition to the Full-On mode.
• T
NOM
is the duration running at f
CCLKNOM
• T
RED
is the duration running at f
CCLKRED
The percent power savings is calculated as:
% Power Savings
=
(
1 –
Power Savings Factor
) ×
100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V
supply.
Figure 7
shows the typical external components
required to complete the power management system.
*
The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(V
DDEXT
) supplied. While in hibernation, V
DDEXT
can still be
applied, eliminating the need for external buffers. The voltage
regulator can be activated from this power-down state either
through an RTC wakeup or by asserting RESET, which will then
initiate a boot sequence. The regulator can also be disabled and
bypassed at the user’s discretion.
Power Savings
As shown in
Table 5,
the ADSP-BF531/2/3 processor supports
three different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compliance
with industry standards and conventions. By isolating the inter-
nal logic of the ADSP-BF531/2/3 processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of Dynamic Power Management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
Table 5. Power Domains
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
VDD Range
V
DDINT
V
DDRTC
V
DDEXT
V
DDEXT
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The Dynamic Power Management feature of the ADSP-
BF531/2/3 processor allows both the processor’s input voltage
(V
DDINT
) and clock frequency (f
CCLK
) to be dynamically
controlled.
The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.
The Power Savings Factor is calculated as:
Power Savings Factor
V
DDINTRED
2
T
RED
f
CCLKRED
-
-
-
= --------------------
×
-------------------------
×
------------
T
NOM
f
CCLKNOM
V
DDINTNOM
100 µF
10 µH
0.1 µF
100 µF
1 µF
ZHCS1000
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
NDS8434
V
DDINT
VR
OUT
1-0
EXTERNAL COMPONENTS
NOTE: VR
OUT
1-0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.
Figure 7. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF531/2/3 processor can be clocked by an external
crystal, a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
where the variables in the equations are:
• f
CCLKNOM
is the nominal core clock frequency
• f
CCLKRED
is the reduced core clock frequency
• V
DDINTNOM
is the nominal internal supply voltage
• V
DDINTRED
is the reduced internal supply voltage
*
See EE-228: Switching Regulator Design Considerations for ADSP-BF533
Blackfin Processors.
Rev. 0 |
Page 12 of 56 | March 2004
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