ADSP-BF531/ADSP-BF532
SDRAM Interface Timing
Table 18. SDRAM Interface Timing1
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min Max Min
Max
Unit
Timing Requirements
tSSDAT
tHSDAT
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
2.1
0.0
1.5
0.8
ns
ns
Switching Characteristics
tSCLK
CLKOUT Period2
10.0
2.5
7.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
tSCLKH
tSCLKL
tDCAD
tHCAD
tDSDAT
tENSDAT
CLKOUT Width High
CLKOUT Width Low
2.5
Command, ADDR, Data Delay After CLKOUT3
Command, ADDR, Data Hold After CLKOUT1
Data Disable After CLKOUT
Data Enable After CLKOUT
6.0
6.0
4.0
4.0
1.0
1.0
1.0
1.0
1 SDRAM timing for TJUNCTION
= 125°C is limited to 100 MHz.
2 Refer to Table 14 on Page 23 for maximum fSCLK at various VDDINT
.
3 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
tSCLKH
CLKOUT
tSSDAT
tSCLKL
tHSDAT
DATA(IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA(OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13. SDRAM Interface Timing
Rev. D
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Page 27 of 60
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August 2006
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