ADSP-BF531/ADSP-BF532/ADSP-BF533
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
RESERVED
INTERNAL MEMORY MAP
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
RESERVED
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (64K BYTE)
0xFFA0 0000
RESERVED
0xFF90
8000
DATA BANK B SRAM/CACHE (16K BYTE)
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
0xFF90 0000
RESERVED
0xFF80
8000
RESERVED
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
DATA BANK A SRAM/CACHE (16K BYTE)
DATA BANK A SRAM (16K BYTE)
0xFF80 0000
RESERVED
RESERVED
0xEF00 0000
EXTERNAL MEMORY MAP
INTERNAL MEMORY MAP
EXTERNAL MEMORY MAP
0xFFB0 0000
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
RESERVED
0xFFA0 C000
INSTRUCTION SRAM (16K BYTE)
0xFFA0
8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90
8000
RESERVED
0xFF90 4000
0xFF80
8000
0xFF80 4000
0xEF00 0000
RESERVED
0x2040 0000
ASYNC MEMORY BANK
3
(1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
RESERVED
0x2040 0000
ASYNC MEMORY BANK
3
(1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
Figure 3. ADSP-BF531 Internal/External Memory Map
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
RESERVED
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
0xFFA0
8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90
8000
DATA BANK B SRAM/CACHE (16K BYTE)
0xFF90 4000
RESERVED
0xFF80
8000
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
RESERVED
0xEF00 0000
0x2040 0000
ASYNC MEMORY BANK
3
(1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
EXTERNAL MEMORY MAP
INTERNAL MEMORY MAP
Figure 5. ADSP-BF533 Internal/External Memory Map
Event Handling
The event controller on the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor handles all asynchronous and synchro
nous events to the processor. The ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor provides event handling that supports
both nesting and prioritization. Nesting allows multiple event
service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut
down of the system.
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
0xFFB0 0000
RESERVED
Figure 4. ADSP-BF532 Internal/External Memory Map
Rev. E |
Page 6 of 60 |
July 2007
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