ADSP-BF531/ADSP-BF532
Programmable Flags Cycle Timing
Table 27 and Figure 25 describe programmable flag operations.
Table 27. Programmable Flags Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max Min
Max
Unit
ns
Timing Requirement
tWFI
Switching Characteristic
tDFO Flag Output Delay from CLKOUT Low
Flag Input Pulse Width
tSCLK + 1
tSCLK + 1
6
6
ns
CLKOUT
tDFO
PF (OUTPUT)
FLAG OUTPUT
FLAG INPUT
tWFI
PF (INPUT)
Figure 25. Programmable Flags Cycle Timing
Rev. D
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Page 40 of 60
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August 2006