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ADSP-BF532WYBCZ-4A 参数 Datasheet PDF下载

ADSP-BF532WYBCZ-4A图片预览
型号: ADSP-BF532WYBCZ-4A
PDF下载: 下载PDF文件 查看货源
内容描述: Blackfin嵌入式处理器 [Blackfin Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 60 页 / 3025 K
品牌: ADI [ ADI ]
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ADSP-BF531/ADSP-BF532  
The power dissipated by a processor is largely a function of the  
clock frequency of the processor and the square of the operating  
voltage. For example, reducing the clock frequency by 25%  
results in a 25% reduction in dynamic power dissipation, while  
reducing the voltage by 25% reduces dynamic power dissipation  
by more than 40%. Further, these power savings are additive, in  
that if the clock frequency and supply voltage are both reduced,  
the power savings can be dramatic.  
VDDEX T  
100µF  
2.25V TO 3.6V  
INPUT VOLTAGE  
RANGE  
10µH  
VDDINT  
0.1µF  
ZHCS1000  
FDS9431A  
100µF  
1µF  
The dynamic power management feature of the ADSP-BF531/  
ADSP-BF532 processor allows both the processor’s input volt-  
age (VDDINT) and clock frequency (fCCLK) to be dynamically  
controlled.  
VROUT10  
EXTERNAL COMPONENT S  
The savings in power dissipation can be modeled using the  
power savings factor and % power savings calculations.  
NOTE: VROUT10 SHOULD BE TIED TOGETHER EXTERNALLY  
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.  
The power savings factor is calculated as:  
Figure 6. Voltage Regulator Circuit  
power savings factor  
If an external clock is used, it must not be halted, changed, or  
operated below the specified frequency during normal opera-  
tion. This signal is connected to the processor’s CLKIN pin.  
When an external clock is used, the XTAL pin must be left  
unconnected.  
2
fCCLKRED  
---------------------  
fCCLKNOM  
VDDINTRED  
--------------------------  
VDDINTNOM  
tRED  
----------  
tNOM  
=
×
×
where the variables in the equations are:  
f
CCLKNOM is the nominal core clock frequency  
CCLKRED is the reduced core clock frequency  
Alternatively, because the ADSP-BF531/ADSP-BF532 processor  
includes an on-chip oscillator circuit, an external crystal may be  
used. The crystal should be connected across the CLKIN and  
XTAL pins, with two capacitors connected as shown in Figure 7.  
Capacitor values are dependent on crystal type and should be  
specified by the crystal manufacturer. A parallel-resonant,  
fundamental frequency, microprocessor-grade crystal should  
be used.  
f
V
V
DDINTNOM is the nominal internal supply voltage  
DDINTRED is the reduced internal supply voltage  
t
NOM is the duration running at fCCLKNOM  
RED is the duration running at fCCLKRED  
t
The percent power savings is calculated as:  
% power savings = (1 power savings factor) × 100%  
VOLTAGE REGULATION  
XTAL  
CLKOUT  
CLKIN  
The Blackfin processor provides an on-chip voltage regulator  
that can generate processor core voltage levels 0.85 V to 1.2 V  
from an external 2.25 V to 3.6 V supply. Figure 6 shows the typ-  
ical external components required to complete the power  
management system.The regulator controls the internal logic  
voltage levels and is programmable with the voltage regulator  
control register (VR_CTL) in increments of 50 mV. To reduce  
standby power consumption, the internal voltage regulator can  
be programmed to remove power to the processor core while  
keeping I/O power (VDDEXT) supplied. While in hibernation,  
Figure 7. External Crystal Connections  
As shown in Figure 8 on Page 14, the core clock (CCLK) and  
system peripheral clock (SCLK) are derived from the input  
clock (CLKIN) signal. An on-chip PLL is capable of multiplying  
the CLKIN signal by a user programmable 0.5× to 64× multipli-  
cation factor (bounded by specified minimum and maximum  
VCO frequencies). The default multiplier is 10×, but it can be  
modified by a software instruction sequence. On-the-fly  
frequency changes can be effected by simply writing to the  
PLL_DIV register.  
V
DDEXT can still be applied, eliminating the need for external  
buffers. The voltage regulator can be activated from this power-  
down state either through an RTC wakeup or by asserting  
RESET, which will then initiate a boot sequence. The regulator  
can also be disabled and bypassed at the user’s discretion.  
CLOCK SIGNALS  
All on-chip peripherals are clocked by the system clock (SCLK).  
The system clock frequency is programmable by means of the  
SSEL3–0 bits of the PLL_DIV register. The values programmed  
The ADSP-BF531/ADSP-BF532 processor can be clocked by an  
external crystal, a sine wave input, or a buffered, shaped clock  
derived from an external clock oscillator.  
See EE-228: Switching Regulator Design Considerations for Blackfin Processors.  
Rev. D  
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Page 13 of 60  
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August 2006