ADSP-BF531/ADSP-BF532
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min Typical Max Unit
VOH
VOH
VOH
VOL
VOL
IIH
High Level Output Voltage1
High Level Output Voltage1
High Level Output Voltage1
Low Level Output Voltage1
Low Level Output Voltage1
High Level Input Current2
High Level Input Current JTAG3
Low Level Input Current2
@ VDDEXT = 1.75 V, IOH = –0.5 mA
1.5
1.9
2.4
V
V
V
V
V
@ VDDEXT = 2.25 V, IOH = –0.5 mA
@ VDDEXT = 3.0 V, IOH = –0.5 mA
@ VDDEXT = 1.75 V, IOL = 2.0 mA
0.2
0.4
@ VDDEXT = 2.25 V/3.0 V, IOL = 2.0 mA
@ VDDEXT = Maximum, VIN = VDD Maximum
@ VDDEXT = Maximum, VIN = VDD Maximum
@ VDDEXT = Maximum, VIN = 0 V
10.0 µA
50.0 µA
10.0 µA
10.0 µA
10.0 µA
IIHP
4
IIL
IOZH
Three-State Leakage Current5
Three-State Leakage Current5
Input Capacitance6
@ VDDEXT = Maximum, VIN = VDD Maximum
@ VDDEXT = Maximum, VIN = 0 V
4
IOZL
CIN
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V)
VDDINT = 0.8 V, TJUNCTION = 25°C
4
87
pF
IDDHIBERNATE
VDDINT Current in Hibernate Mode
VDDINT Current in Deep Sleep Mode
VDDINT Current in Sleep Mode
VDDINT Current Dissipation (Typical)
VDDINT Current Dissipation (Typical)
VDDRTC Current
50
7.5
10
20
132
20
µA
8
IDDDEEPSLEEP
mA
mA
mA
mA
µA
IDDSLEEP
VDDINT = 0.8 V, TJUNCTION = 25°C
8, 9
IDD
VDDINT = 0.8 V, fIN = 50 MHz, TJUNCTION = 25°C
VDDINT = 1.14 V, fIN = 400 MHz, TJUNCTION = 25°C
VDDRTC = 3.3 V, TJUNCTION = 25°C
_
_
TYP
TYP
8, 9
IDD
IDDRTC
1 Applies to output and bidirectional pins.
2 Applies to input pins except JTAG inputs.
3 Applies to JTAG input pins (TCK, TDI, TMS, TRST).
4 Absolute value.
5 Applies to three-statable pins.
6 Applies to all signal pins.
7 Guaranteed, but not tested.
8 See Power Dissipation on Page 45.
9 Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.
Rev. D
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Page 21 of 60
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August 2006
ADI [ ADI ]
