欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADSP-BF531WBBZ-4A 参数 Datasheet PDF下载

ADSP-BF531WBBZ-4A图片预览
型号: ADSP-BF531WBBZ-4A
PDF下载: 下载PDF文件 查看货源
内容描述: Blackfin㈢嵌入式处理器 [Blackfin㈢ Embedded Processor]
分类和应用:
文件页数/大小: 60 页 / 3447 K
品牌: AD [ ANALOG DEVICES ]
更多
  •  
  • 供货商
  • 型号*
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第2页浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第3页浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第4页浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第5页浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第6页浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第7页浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第8页浏览型号ADSP-BF531WBBZ-4A的Datasheet PDF文件第9页 
Blackfin
®
Embedded Processor
ADSP-BF531/ADSP-BF532/ADSP-BF533
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro­
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.85 V to 1.30 V core V
DD
with on-chip voltage regulation
1.8 V, 2.5 V, and 3.3 V compliant I/O
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP
packages
External memory controller with glueless support for
SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI
®
and
external memory
PERIPHERALS
Parallel peripheral interface PPI/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, sup­
porting eight stereo I
2
S channels
Four memory-to-memory DMAs
Eight peripheral DMAs
SPI-compatible port
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA
®
Event handler
Debug/JTAG interface
On-chip PLL capable of 0.5�½ to 64�½ frequency multiplication
MEMORY
Up to 148K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
Up to 64K bytes of instruction SRAM
Up to32K bytes of data SRAM/Cache
Up to32K bytes of data SRAM
4K bytes of scratchpad SRAM
Memory management unit providing memory protection
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
B
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
INTERRUPT
CONTROLLER
PERIPHERAL ACCESS BUS
WATCHDOG
TIMER
RTC
PPI
DMA
CONTROLLER
DMA ACCESS BUS
TIMER0-2
SPI
UART
SPORT0-1
DMA CORE BUS
EXTERNAL ACCESS BUS
DMA
EXTERNAL
BUS
GPIO
PORT
F
EXTERNAL PORT
FLASH, SDRAM CONTROL
16
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2007
Analog Devices, Inc. All rights reserved.