Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
RISC-like register and instruction model for ease of pro
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.85 V to 1.30 V core V
with on-chip voltage regulation
1.8 V, 2.5 V, and 3.3 V compliant I/O
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP
External memory controller with glueless support for
SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI
Parallel peripheral interface PPI/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, sup
porting eight stereo I
Four memory-to-memory DMAs
Eight peripheral DMAs
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA
On-chip PLL capable of 0.5�½ to 64�½ frequency multiplication
Up to 148K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
Up to 64K bytes of instruction SRAM
Up to32K bytes of data SRAM/Cache
Up to32K bytes of data SRAM
4K bytes of scratchpad SRAM
Memory management unit providing memory protection
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
DMA ACCESS BUS
DMA CORE BUS
EXTERNAL ACCESS BUS
FLASH, SDRAM CONTROL
Figure 1. Functional Block Diagram
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