Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core V
with on-chip voltage regulation
1.8 V, 2.5 V, and 3.3 V compliant I/O
160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead
External memory controller with glueless support for
SDRAM, SRAM, FLASH, and ROM
Flexible memory booting options from SPI
Parallel peripheral interface PPI/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, sup-
porting eight stereo I
12-channel DMA controller
Three timer/counters with PWM support
UART with support for IrDA
On-chip PLL capable of 0.5 to 64 frequency multiplication
Up to 84K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
32K bytes of instruction SRAM
32K bytes of data SRAM/Cache
4K bytes of scratchpad SRAM
Two dual-channel memory DMA controllers
Memory management unit providing memory protection
JTAG TEST AND
CORE/SYSTEM BUS INTERFACE
PPI / GPIO
SERIAL PORTS (2)
Figure 1. Functional Block Diagram
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