ADSP-BF531/ADSP-BF532
20
RISE AND FALL TIME ns (10% to 90%)
18
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
0
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
TMR0 (33MHz DRIVER), V
DDEXT
(MAX) =
3.65V
RISE AND FALL TIME ns (10% to 90%)
14
SCK
(66MHz DRIVER), V
DDEXT
(MAX) =
3.65V
12
10
RISE TIME
8
FALL TIME
6
4
2
Figure 51. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at V
DDEXT
= 3.65 V
SCK
(66MHz DRIVER), V
DDEXT
= 1.7V
Figure 54. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at V
DDEXT
= 3.65 V
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
T
J
=
T
CASE
+
( Ψ
JT
×
P
D
)
where:
18
RISE AND FALL TIME ns (10% to 90%)
16
RISE TIME
14
12
10
8
6
4
2
0
FALL TIME
T
J
= junction temperature ( C).
T
CASE
= case temperature ( C) measured by customer at top
center of package.
Ψ
JT
= from
through
P
D
= power dissipation (see
for
the method to calculate
P
D
).
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Values of
θ
JA
are provided for package comparison and printed
circuit board design considerations.
θ
JA
can be used for a first
order approximation of
T
J
by the equation:
T
J
=
T
A
+
( θ
JA
×
P
D
)
where:
T
A
= ambient temperature ( C).
In
through
airflow measurements comply
with JEDEC standards JESD51–2 and JESD51–6, and the junc-
tion-to-board measurement complies with JESD51–8. The
junction-to-case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
Figure 52. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at V
DDEXT
= 1.8 V
SCK
(66MHz DRIVER), V
DDEXT
(MIN) = 2.25V
18
RISE AND FALL TIME ns (10% to 90%)
16
14
RISE TIME
12
10
FALL TIME
8
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 53. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at V
DDEXT
= 2.25 V
Rev. D |
Page 48 of 60 |
August 2006
AD [ ANALOG DEVICES ]
