ADSP-BF531/ADSP-BF532/ADSP-BF533
Timer Clock Timing
Table 35 and Figure 30 describe timer clock timing.
Table 35. Timer Clock Timing
Parameter
Min
Max
Unit
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
12
ns
PPI_CLK
tTODP
TMRx OUTPUT
Figure 30. Timer Clock Timing
Timer Cycle Timing
Table 36 and Figure 31 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 36. Timer Cycle Timing
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Min
Max
Unit
Timing Characteristics
tWL Timer Pulse Width Low1
tWH Timer Pulse Width High1
tTIS Timer Input Setup Time Before CLKOUT Low2
tTIH Timer Input Hold Time After CLKOUT Low2
Switching Characteristics
1 × tSCLK
1 × tSCLK
8.0
1 × tSCLK
1 × tSCLK
6.5
ns
ns
ns
ns
1.5
1.5
tHTO Timer Pulse Width Output
tTOD Timer Output Update Delay After CLKOUT High
1 × tSCLK (232–1) × tSCLK 1 × tSCLK (232–1) × tSCLK ns
7.5 6.5 ns
1 The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 31. Timer PWM_OUT Cycle Timing
Rev. I
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Page 41 of 64
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August 2013
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