ADSP-BF531/ADSP-BF532/ADSP-BF533
The following three tables describe the voltage/frequency
requirements for the processor clocks. Take care in selecting
core clock (Table 10 and Table 11) and system clock (Table 13)
specifications. Table 12 describes phase-locked loop operating
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
Table 10. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models
Parameter Internal Regulator Setting Max
conditions.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fCCLK CCLK Frequency (VDDINT = 1.3 V Minimum)1 1.30 V
fCCLK CCLK Frequency (VDDINT = 1.2 V Minimum)2 1.25 V
fCCLK CCLK Frequency (VDDINT = 1.14 V Minimum)3 1.20 V
fCCLK CCLK Frequency (VDDINT = 1.045 V Minimum) 1.10 V
fCCLK CCLK Frequency (VDDINT = 0.95 V Minimum) 1.00 V
fCCLK CCLK Frequency (VDDINT = 0.85 V Minimum) 0.90 V
fCCLK CCLK Frequency (VDDINT = 0.8 V Minimum) 0.85 V
1 Applies to 600 MHz models only. See Ordering Guide on Page 63.
600
533
500
444
400
333
250
2 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 63. 533 MHz models cannot support internal regulator levels above 1.25 V.
3 Applies to 500 MHz, 533 MHz, and 600 MHz models. See Ordering Guide on Page 63. 500 MHz models cannot support internal regulator levels above 1.20 V.
Table 11. Core Clock (CCLK) Requirements—400 MHz Models1
TJ = 125°C
Internal Regulator Setting Max
All2 Other TJ
Max
Parameter
Unit
MHz
MHz
MHz
MHz
MHz
fCCLK CCLK Frequency (VDDINT = 1.14 V Minimum) 1.20 V
fCCLK CCLK Frequency (VDDINT = 1.045 V Minimum) 1.10 V
fCCLK CCLK Frequency (VDDINT = 0.95 V Minimum) 1.00 V
fCCLK CCLK Frequency (VDDINT = 0.85 V Minimum) 0.90 V
fCCLK CCLK Frequency (VDDINT = 0.8 V Minimum) 0.85 V
400
333
295
400
364
333
280
250
1 See Ordering Guide on Page 63.
2 See Operating Conditions on Page 20.
Table 12. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO Voltage Controlled Oscillator (VCO) Frequency
50
Max fCCLK
MHz
Table 13. System Clock (SCLK) Requirements
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter1
Max
Max
Unit
CSP_BGA/PBGA
fSCLK
fSCLK
LQFP
fSCLK
fSCLK
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
100
100
133
100
MHz
MHz
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
100
83
133
83
MHz
MHz
1 tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK
.
Rev. I
|
Page 21 of 64
|
August 2013
ADI [ ADI ]
