欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADSP-21065LKS-240 参数 Datasheet PDF下载

ADSP-21065LKS-240图片预览
型号: ADSP-21065LKS-240
PDF下载: 下载PDF文件 查看货源
内容描述: 微电脑DSP [DSP Microcomputer]
分类和应用: 外围集成电路电脑时钟
文件页数/大小: 44 页 / 489 K
品牌: AD [ ANALOG DEVICES ]
 浏览型号ADSP-21065LKS-240的Datasheet PDF文件第2页浏览型号ADSP-21065LKS-240的Datasheet PDF文件第3页浏览型号ADSP-21065LKS-240的Datasheet PDF文件第4页浏览型号ADSP-21065LKS-240的Datasheet PDF文件第5页浏览型号ADSP-21065LKS-240的Datasheet PDF文件第6页浏览型号ADSP-21065LKS-240的Datasheet PDF文件第7页浏览型号ADSP-21065LKS-240的Datasheet PDF文件第8页浏览型号ADSP-21065LKS-240的Datasheet PDF文件第9页  
a
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC
®
)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
2
I S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
DSP Microcomputer
ADSP-21065L
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
DUAL-PORTED SRAM
BLOCK 1
CORE PROCESSOR
INSTRUCTION
CACHE
32
48 BIT
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
ADDR
DATA
DATA
BLOCK 0
JTAG
TEST &
EMULATION
7
I/O PORT
DATA
ADDR
ADDR
DATA
DAG1
8
4
32
8
DAG2
4
24
PROGRAM
SEQUENCER
24
32
PM ADDRESS BUS
DM ADDRESS BUS
IOA
17
IOD
48
EXTERNAL
PORT
SDRAM
INTERFACE
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
24
48
PM DATA BUS
DATA BUS
MUX
HOST PORT
32
BUS
CONNECT
(PX)
40 DM DATA BUS
DATA
REGISTER
FILE
MULTIPLIER
16
40 BIT
IOP
REGISTERS
(MEMORY MAPPED)
DMA
CONTROLLER
SPORT 0
4
(2 Rx, 2Tx)
(I
2
S)
(2 Rx, 2Tx)
BARREL
SHIFTER
ALU
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
SPORT 1
(I
2
S)
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.