ADM705/ADM706/ADM707/ADM708
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
MR
1
V
CC 2
GND
3
ADM705/
ADM706
8
7
WDO
RESET
MR
1
V
CC 2
GND
3
00088-003
ADM707/
ADM708
8
7
RESET
RESET
RESET
RESET
MR
00088-004
1
2
3
4
ADM708
8
7
NC
PFO
V
CC
NC = NO CONNECT
NC = NO CONNECT
Figure 3. ADM705/ADM706 PDIP/SOIC
Pin Configuration
Figure 4. ADM707/ADM708 PDIP/SOIC
Pin Configuration
Figure 5. ADM708 MSOP
Pin Configuration
Table 3. Pin Function Descriptions
ADM705/
ADM706
(PDIP, SOIC)
1
Pin Number
ADM707/
ADM708
(PDIP, SOIC)
1
Mnemonic
MR
ADM708
(MSOP)
3
V
CC
GND
PFI
2
3
4
2
3
4
4
5
6
PFO
WDI
5
6
5
N/A
7
N/A
NC
RESET
N/A
7
6
7
8
1
WDO
8
N/A
N/A
RESET
N/A
8
2
Description
Manual Reset Input. When this pin is taken below 0.8 V, a reset is generated.
MR can be driven from TTL, CMOS logic, or from a manual reset switch as it is
internally debounced. An internal 250 μA pull-up current holds the input high
when floating.
5 V Power Supply Input.
0 V Ground Reference for All Signals.
Power-Fail Input. PFI is the noninverting input to the power-fail comparator.
When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND or V
CC
.
Power-Fail Output. PFO is the output from the power-fail comparator. It goes
low when PFI is less than 1.25 V.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output (WDO)
goes low. The timer resets with each transition at the WDI input. Either a high-
to-low or a low-to-high transition clears the counter. The internal timer is also
cleared whenever reset is asserted. The watchdog timer is disabled when WDI
is left floating or connected to a three-state buffer.
No Connect.
Logic Output. RESET goes low for 200 ms when triggered. It can be trig-
gered either by V
CC
being below the reset threshold or by a low signal on the
manual reset input (MR). RESET remains low whenever V
CC
is below the reset
threshold (4.65 V in ADM705/ADM707, 4.40 V in ADM706/ADM708). It remains
low for 200 ms after V
CC
goes above the reset threshold or MR goes from low to
high. A watchdog timeout does not trigger RESET unless WDO is connected to MR.
Watchdog Output. WDO remains low until the watchdog timer is cleared. WDO
also goes low during low line conditions. Whenever V
CC
is below the reset
threshold, WDO goes low if the internal WDO remains low. As soon as V
CC
goes
above the reset threshold, WDO goes high.
Logic Output. RESET is an active high output suitable for systems that use
active high reset logic. It is the inverse of RESET.
Rev. G | Page 5 of 12
00088-005
6
WDI
TOP VIEW
(Not to Scale)
5
PFO
PFI
4
6
NC
TOP VIEW
(Not to Scale)
5
PFO
PFI
4
6
PFI
TOP VIEW
(Not to Scale)
5
GND
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