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ADM708TAR 参数 Datasheet PDF下载

ADM708TAR图片预览
型号: ADM708TAR
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V ,电压监控微处理器监控电路 [3 V, Voltage Monitoring Microprocessor Supervisory Circuits]
分类和应用: 微处理器监控
文件页数/大小: 16 页 / 333 K
品牌: AD [ ANALOG DEVICES ]
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ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
MR
1
V
CC 2
GND
3
8
WDO
RESET
MR
1
V
CC 2
GND
3
06435-003
ADM706P
7
Figure 3. ADM706P
Figure 4. ADM706R/ADM706S/ADM706T
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T
Pin No.
1
Mnemonic
MR
Description
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven
from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An
internal 70 μA pull-up current holds the input high when floating.
Power Supply Input.
Ground. Ground reference for all signals (0 V).
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less
than 1.25 V, PFO goes low. If unused, PFI should be connected to GND.
Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is
less than 1.25 V.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI
input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is
also cleared whenever reset is asserted.
Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by V
CC
being
below the reset threshold or by a low signal on the MR input. RESET remains low whenever V
CC
is below the reset threshold. It remains low for 200 ms after V
CC
goes above the reset threshold
or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is
connected to MR.
Logic Output. RESET is an active high output suitable for systems that use active high reset
logic. It is the inverse of RESET.
Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of
inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes
low during low line conditions. Whenever V
CC
is below the reset threshold, WDO remains low. As
soon as V
CC
goes above the reset threshold, WDO goes high immediately.
2
3
4
5
6
V
CC
GND
PFI
PFO
WDI
7 (ADM706R/ADM706S/
ADM706T Only)
RESET
7 (ADM706P Only)
8
RESET
WDO
Rev. C | Page 6 of 16
06435-004
6
WDI
TOP VIEW
PFI
4
(Not to Scale)
5
PFO
PFI
4
6
WDI
TOP VIEW
5
PFO
(Not to Scale)
ADM706R/
ADM706S/
ADM706T
8
7
WDO
RESET