ADM706P/R/S/T, ADM708R/S/T
V
CC
= +5V
T
A
= +25 C
1.3V
PFI
+1.2V
+3V
+3V
+3V
RESET
RESET
V
CC
= V
RT
T
A
= +25 C
PFO
0V
0V
0V
500ns/DIV
100ns/DIV
Figure 10. PFI Assertion Response Time
Figure 13.
RESET
, RESET Deassertion
T
A
= +25 C
+3V
V
CC
+1.3V
PFI
+2V
V
CC
= +5V
T
A
= +25 C
1.2V
+3V
+3V
RESET
PFO
0V
0V
500ns/DIV
2 s/DIV
Figure 11. PFI Deassertion Response Time
Figure 14. ADM706/ADM708
RESET
Response Time
V
CC
= V
RT
T
A
= +25 C
APPLICATIONS
+3V
+3V
RESET
RESET
A typical operating Circuit is shown in Figure 15. The unregu-
lated dc input supply is monitored using the PFI input via the
resistive divider network. Resistors R1 and R2 should be selected
such that when the supply voltage drops below the desired level
(e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold
thereby generating an interrupt to the
µP.
Monitoring the
preregulator input gives additional time to execute an orderly
shutdown procedure before power is lost.
ADM666A
IN
GND
OUT
+3.3V
0V
0V
UNREGULATED
DC
100ns/DIV
Figure 12.
RESET
, RESET Assertion
PFI
MR
V
CC
RESET
WDI
V
CC
RESET
I/O LINE
ADM706
WDO
PFO
GND
MANUAL
RESET
NMI
P
INTERRUPT
GND
Figure 15. Typical Application Circuit
REV. A
–7–
AD [ ANALOG DEVICES ]
