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ADM706TAR 参数 Datasheet PDF下载

ADM706TAR图片预览
型号: ADM706TAR
PDF下载: 下载PDF文件 查看货源
内容描述: +3 V ,电压监控多达监控电路 [+3 V, Voltage Monitoring uP Supervisory Circuits]
分类和应用: 电源电路电源管理电路光电二极管监控输入元件
文件页数/大小: 8 页 / 128 K
品牌: AD [ ANALOG DEVICES ]
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ADM706P/R/S/T, ADM708R/S/T
PIN FUNCTION DESCRIPTIONS
Mnemonic
MR
Pin No.
ADM706
1
Pin No.
ADM708
1
Function
Manual Reset Input. When taken below 0.6 V a RESET is generated.
MR
can be
driven from TTL, CMOS logic or from a manual reset switch as it is internally
debounced. An internal 70
µA
pull-up current holds the input high when floating.
Power Supply Input.
0 V. Ground reference for all signals.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator.
When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND.
Power Fail Output.
PFO
is the output from the Power Fail Comparator. It goes
low when PFI is less than 1.25 V.
Watchdog Input. WDI is a three level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output
WDO
goes
low. The timer resets with each transition at the WDI input. Either a high-to-low
or a low-to-high transition will clear the counter. The internal timer is also
cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is
left floating or connected to a three-state buffer.
No Connect.
Logic Output.
RESET
goes low for 200 ms when triggered. It can be triggered
either by V
CC
being below the reset threshold or by a low signal on the manual
reset (MR) input.
RESET
will remain low whenever V
CC
is below the reset
threshold. It remains low for 200 ms after V
CC
goes above the reset threshold or
MR
goes from low to high. A watchdog timeout will not trigger
RESET
unless
WDO
is connected to
MR.
Logic Output. RESET is an active high output suitable for systems which use
active high RESET logic. It is the inverse of
RESET.
Logic Output. The Watchdog Output,
WDO,
goes low if the internal watchdog
timer times out as a result of inactivity on the WDI input. It remains low until
the watchdog timer is cleared.
WDO
also goes low during low line conditions.
Whenever V
CC
is below the reset threshold,
WDO
remains low. As soon as V
CC
goes above the reset threshold,
WDO
goes high immediately.
PIN CONFIGURATIONS
V
CC
GND
PFI
2
3
4
2
3
4
PFO
WDI
5
6
5
N/A
NC
RESET
N/A
7 (R/S/T Only)
6
7
RESET
WDO
7 (P Only)
8
8
N/A
MR
V
CC
GND
PFI
1
2
3
4
8
WDO
MR
V
CC
GND
PFI
1
2
3
4
8
WDO
MR
V
CC
GND
PFI
1
2
3
4
8 RESET
ADM706
P
7 RESET
6 WDI
TOP VIEW
(Not to Scale) 5
PFO
6 WDI
TOP VIEW
(Not to Scale) 5
PFO
ADM706
R/S/T
7
RESET
ADM708
R/S/T
7
RESET
6 NC
TOP VIEW
(Not to Scale) 5
PFO
NC = NO CONNECT
–4–
REV. A