Data Sheet
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
MR
1
V
CC 2
GND
3
PFI
4
NC = NO CONNECT
Figure 5.
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
MR
Description
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS
logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds
the input high when floating.
Power Supply Input. Place a 0.1 µF decoupling capacitor between the V
CC
and GND pins.
Ground. Ground reference for all signals (0 V).
Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less than 1.25 V, PFO
goes low. If unused, PFI must connect to GND.
Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25 V.
No Connect.
Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by V
CC
being below the reset
threshold or by a low signal on the MR input. RESET remains low whenever V
CC
is below the reset threshold. It
remains low for 200 ms after V
CC
goes above the reset threshold or MR goes from low to high. A watchdog
timeout does not trigger RESET unless WDO is connected to MR.
Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the
inverse of RESET.
2
3
4
5
6
7
V
CC
GND
PFI
PFO
NC
RESET
8
RESET
Rev. E | Page 7 of 16
06435-005
6
NC
TOP VIEW
5
PFO
(Not to Scale)
ADM708R/
ADM708S/
ADM708T
8
7
RESET
RESET
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