ADM690–ADM695
R =(VCC – 50 mV)/1 µA
+5V
Note that the resistor will discharge the battery slightly. With a
VCC supply of 4.5 V, a suitable resistor is 4.3 MΩ. With a 3 V
battery this will draw around 700 nA. T his will be negligible in
most cases.
R1
VCC
µP POWER
CMOS RAM
VOUT
PFI
POWER
ADM690
ADM692
ADM694
0.1µF
µP SYSTEM
R2
V
BATT
µP RESET
µP NMI
RESET
PFO
BATTERY
R
VBATT
+
ADM69x
BATTERY
I/O LINE
WDI
GND
Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A
Figure 22b. Preventing Spurious RESETS During Battery
Replacem ent
Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. T his gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or
TYP ICAL AP P LICATIO NS
AD M690, AD M692 AND AD M694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. VOUT powers the
CMOS RAM. Under normal operating conditions with VCC
present, VOUT is internally connected to VCC. If a power failure
occurs, VCC will decay and VOUT will be switched to VBAT T
thereby maintaining power for the CMOS RAM. A RESET
pulse is also generated when VCC falls below 4.65 V for the
ADM690/ADM694 or 4.4 V for the ADM692. RESET will
remain low for 50 ms (200 ms for ADM694) after VCC returns
to 5 V.
where there are a significant number of housekeeping tasks to be
completed before the power is lost.
+5V
7805
INPUT
POWER
V > 8V
0.1µF
R
1
2
V
µP POWER
CMOS RAM
CC
V
OUT
PFI
POWER
ADM690
ADM692
ADM694
0.1µF
µP SYSTEM
R
T he watchdog timer input (WDI) monitors an I/O line from the
µP system. T his line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
µP RESET
µP NMI
RESET
V
BATT
PFO
BATTERY
I/O LINE
WDI
GND
If the watchdog timer is not needed, the WDI input should be
left floating.
Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B
T he Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. T he voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (PFO) signal is
generated. T his warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. T he resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT .
AD M691, AD M693, AD M695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from VOUT . When
5 V power is present this is routed to VOUT . If VCC fails then
VBAT T is routed to VOUT . VOUT can supply up to 100 mA from
VCC, but if more current is required, an external PNP transistor
can be added. When VCC is higher than VBAT T , the BAT T ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 µF capacitor is connected to VOUT to
supply the transient currents for CMOS RAM. When VCC is
lower than VBAT T , an internal 20 Ω MOSFET connects the
VT = (1.3 R1/R2) + 1.3 V
R1/R2 = (VT/1.3) – 1
backup battery to VOUT
.
–12–
REV. A
ADI [ ADI ]
