ADM690–ADM695
CE
Gating and RAM Write Protection (ADM691/ADM693/
ADM695)
Power Fail Warning Comparator
The ADM691/ADM693/ADM695 products include memory
protection circuitry which ensures the integrity of data in mem-
ory by preventing write operations when V
CC
is at an invalid
level. There are two additional pins,
CE
IN
and
CE
OUT
, which
may be used to control the Chip Enable or Write inputs of
CMOS RAM. When V
CC
is present,
CE
OUT
is a buffered replica
of
CE
IN
, with a 5 ns propagation delay. When V
CC
falls below
the reset voltage threshold or V
BATT
, an internal gate forces
CE
OUT
high, independent of
CE
IN
.
CE
OUT
typically drives the
CE, CS,
or write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
CC
is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the
CE
OUT
to drive the store or write inputs.
If the 5 ns typical propagation delay of
CE
OUT
is excessive, con-
nect
CE
IN
to GND and use the resulting
CE
OUT
to control a
high speed external logic gate.
ADM69x
CE
IN
CE
OUT
An additional comparator is provided for early warning of failure
in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V sev-
eral milliseconds before the +5 V power supply falls below the
reset threshold.
PFO
is normally used to interrupt the micropro-
cessor so that data can be stored in RAM and the shut down
procedure executed before power is lost
INPUT
POWER
R
1
1.3V
POWER
FAIL
INPUT
PFO
POWER
FAIL
OUTPUT
R
2
ADM69x
V
CC
LOW = 0
V
CC
OK = 1
Figure 7. Power Fail Comparator
Table II. Input and Output Status In Battery Backup Mode
Figure 5. Chip Enable Gating
V
CC
V2
V1
V2
V1
Signal
Status
V
OUT
RESET
V
OUT
is connected to V
BATT
via an internal
PMOS switch.
Logic low.
Logic high. The open circuit output voltage is
equal to V
OUT
.
Logic low.
Logic high. The open circuit voltage is equal to
V
OUT.
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and V
OUT
. The input voltage
does not affect supply current.
Logic high. The open circuit voltage is equal
to V
OUT
.
The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
Logic low.
CE
IN
is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and V
OUT
. The input voltage
does not affect supply current.
Logic high. The open circuit voltage is equal to
V
OUT
.
OSC IN is ignored.
OSC SEL is ignored.
REV. A
RESET
t
1
t
1
RESET
LOW LINE
LOW LINE
BATT ON
WDI
CE
IN
WDO
CE
OUT
PFI
t
1
= RESET TIME.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
PFO
CE
IN
Figure 6. Chip Enable Timing
CE
OUT
OSC IN
OSC SEL
–8–
AD [ ANALOG DEVICES ]
