ADM690–ADM695
+5V INPUT
POWER
CONTROL
INPUT*
OSC SEL
V
V
CC
BATT
PFO
ADM69x
D1
D2
LOW BATTERY
SIGNAL TO
µP I/O PIN
10MΩ
10MΩ
BATTERY
ADM69x
PFI
OSC IN
CE
IN
20kΩ
OPTIONAL
TEST LOAD
FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY
CE
OUT
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 21b. Program m ing the Watchdog Input
Figure 20. Monitoring the Battery Status
Replacing the Backup Batter y
Alter nate Watchdog Input D r ive Cir cuits
When changing the backup battery with system power on, spuri-
ous resets can occur when the battery is removed. T his occurs
because the leakage current flowing out of the VBAT T pin will
charge up the stray capacitance. If the voltage on VBAT T reaches
within 50 mV of VCC, a reset pulse is generated.
T he watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a 3-state buffer (Figure 21a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
WATCHDOG
STROBE
WDI
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following
solutions should be considered:
ADM69x
CONTROL
INPUT
1. A capacitor from VBAT T to GND. T his gives time while the
capacitor is charging up to replace the battery. T he leakage
current will charge up the external capacitor towards the VCC
level. T he time taken is related to the charging current, the
size of external capacitor and the voltage differential between
the capacitor and the charging voltage supply.
Figure 21a. Program m ing the Watchdog Input
T his circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. T his would
then prevent the ADM69x from detecting that the microproces-
sor is no longer operating correctly. In most cases a better
method is to extend the watchdog period rather than disabling
the watchdog. T his may be done under program control using
the circuit shown in Figure 21b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 µF capacitor sets a watchdog timeout
delay of 100 seconds. When the control input is low, the OSC
SEL pin is driven high, selecting the internal oscillator. T he
100 ms or the 1.6 s period is chosen, depending on which diode
in Figure 21b is used. With D1 inserted the internal timeout is
set at 100 ms, while with D2 inserted the timeout is set at 1.6 s.
t = CEXT × VDIFF/I
T he maximum leakage (charging) current is 1 µA over tem-
perature and VDIFF = VCC–VBAT T. T herefore, the capacitor
size should be chosen such that sufficient time is available to
make the battery replacement.
CEXT = TREQD (1 µA/(VCC–VBATT))
If a replacement time of 5 seconds is allowed and assuming a
VCC of 4.5 V and a VBAT T of 3 V
CEXT = 3.33 µF
VBATT
CEXT
BATTERY
ADM69x
Figure 22a. Preventing Spurious RESETS During
Battery Replacem ent
2. A resistor from VBAT T to GND. T his will prevent the voltage
on VBAT T from rising to within 50 mV of VCC during battery
replacement.
REV. A
–11–
ADI [ ADI ]
