ADM691A/ADM693A/ADM800L/M
PIN DESCRIPTIONS
Pin
1
2
Mnemonic
V
BATT
V
OUT
Function
Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is
not used.
Output Voltage, V
CC
or V
BATT
is internally switched to V
OUT
depending on which is at the highest poten-
tial. When V
CC
is higher than V
BATT
and is also higher than the reset threshold, V
CC
is switched to V
OUT
.
When V
CC
is lower than V
BATT
and below the reset threshold, V
BATT
is switched to V
OUT
. Connect V
OUT
to
V
CC
if a backup battery is not being used.
Power Supply Input; +5 V.
0 V. Ground reference for all signals.
Logic Output. BATT ON goes high when V
OUT
is internally switched to the V
BATT
input. It goes low when
V
OUT
is internally switched to V
CC
. The output may also be used to drive the base (via a resistor) of an ex-
ternal PNP transistor to increase the output current above the 250 mA rating of V
OUT
.
Logic Output.
LOW LINE
goes low when V
CC
falls below the reset threshold. It returns high as soon as
V
CC
rises above the reset threshold.
Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset
delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating
selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external ca-
pacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the
watchdog timeout period. (See Table II and Figure 4.)
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil-
lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator
input, OSC IN, is enabled. OSC SEL has a 10
µA
internal pullup.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than
1.25 V,
PFO
goes low. Connect PFI to GND or V
OUT
when not used.
Power Fail Output.
PFO
is the output of the Power Fail Comparator. It goes low when PFI is less than
1.25 V.
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch-
dog timeout period,
RESET
pulses low and
WDO
goes low. The timer resets with each transition on the
WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.
Output.
CE
OUT
goes low only when
CE
IN
is low and V
CC
is above the reset threshold. If CE
IN
is low when
reset is asserted, CE
OUT
will remain low for 15
µs
or until CE
IN
goes high, whichever occurs first.
Chip Enable Input. The input to the CE gating circuit. Connect to GND or V
OUT
if not used.
Logic Output. The Watchdog Output,
WDO,
goes low if WDI remains either high or low for longer than
the Watchdog timeout period.
WDO
is set high by the next transition at WDI. WDO remains high if WDI
is unconnected.
Logic Output.
RESET
goes low if V
CC
falls below the Reset Threshold. It remains low for 200 ms typ after
V
CC
goes above the reset threshold.
Logic Output. RESET is an open-drain output. It is the inverse of
RESET.
3
4
5
V
CC
GND
BATT ON
6
7
LOW LINE
OSC IN
8
OSC SEL
9
10
11
PFI
PFO
WDI
12
13
14
CE
OUT
CE
IN
WDO
15
16
RESET
RESET
PIN CONFIGURATIONS
V
BATT
V
OUT
V
CC
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
1
2
3
4
5
6
16 RESET
15
RESET
ADM691A
ADM693A
ADM800L
ADM800M
14
WDO
13
CE
IN
12
CE
OUT
11 WDI
TOP VIEW
7 (Not to Scale) 10
PFO
8
9
PFI
–4–
REV. 0
AD [ ANALOG DEVICES ]
