ADM485E/ADM487E/ADM1487E
TIMING SPECIFICATIONS
VCC = 5 V 5ꢀ, TA = TMIN to TMAX, unless otherwise noted.
Table 3. ADM485E/ADM1487E
Parameter
DRIVER
Symbol Min
Typ Max
Unit
Test Conditions/Comments
Input to Output
tDPLH
10
10
40
40
5
60
60
10
40
ns
ns
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
tDPHL
Output Skew to Output
Rise/Fall Time
tSKEW
tDR, tDF
3
20
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
tDZH
tDZL
tDLZ
tDHZ
45
45
45
45
70
70
70
70
ns
ns
ns
ns
CRL = 100 pF, S2 closed (see Figure 21)
CRL = 100 pF, S1 closed (see Figure 22)
CRL = 15 pF, S1 closed (see Figure 22)
CRL = 15 pF, S2 closed (see Figure 21)
Input to Output
tRPLH
tSKEW
20
60
5
200
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 23 and Figure 24)
|tPLH − tPHL| Differential Receiver Skew
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 4 and Figure 5)
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
MAXIMUM DATA RATE
tRZL
tRZL
tRLZ
tRHZ
fMAX
25
20
20
20
50
50
50
50
ns
ns
ns
ns
CRL = 15 pF, S2 closed (see Figure 25)
CRL = 15 pF, S1 closed (see Figure 25)
CRL = 15 pF, S2 closed (see Figure 25)
tPLH, tPHL < 50% of data period
2.5
Mbps
Rev. 0 | Page 4 of 16
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