55
ASM483ꢀ
TꢀET5CIꢅCUITE5ANS5EWITCHING5CHAꢅACTꢀꢅIETICE5
Y
V
CC
R
= 500Ω
L
S1
R
L
0V OR 5V
OUT
D
C
L
V
OD
V
OC
R
L
GENERATOR
50Ω
Z
Figure 15. Driver DC Test Load
5V
0V
DE
V
/2
5V
DE
CC
tDZL,
tDZL(SHDN)
tDLZ
C
C
L
L
V
A
B
CC
OUT
2.3V
DI
V
R
L
OD
0.5V
V
OL
Figure 19. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN)
)
RECEIVER
OUTPUT
B
A
Figure 16. Driver Timing Test Circuit
V
ATE
ID
R
5V
DI
1.5V
0V
tDPLH
tDPHL
1/2 V
O
Figure 20. Receiver Propagation Delay Test Circuit
+1V
B
A
A
B
V
O
–1V
tRPHL
tRPLH
1/2V
O
V
= V (A) – V (B)
DIFF
V
OH
+V
O
RO
V
90%
90%
1.5V
DIFF
0V
–V
V
10%
10%
OL
O
tDR
tDF
THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns
tSKEW
= tDPLH – tDPHL
Figure 21. Receiver Propagation Delays
Figure 17. Driver Propagation Delays
S1
0 OR 5V
D
OUT
C
L
R
= 500Ω
L
GENERATOR
50Ω
5V
0V
DE
1.5V
tDZH,
tDZH(SHDN)
0.5V
V
OH
OUT
2.3V
0V
tDHZ
Figure 18. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN)
)
Rev. A | Page 9 of 16
ADI [ ADI ]
