ADM483E
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RO
1
RE
2
DE
3
8
ADM483E
V
CC
B
GND
06012-002
7
6
5
TOP VIEW
DI
4
(Not to Scale)
A
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
RO
RE
DE
DI
GND
A
B
V
CC
Description
Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low.
Receiver Output Enable. A low level enables the receiver output, RO. A high level places the receiver output in a high
impedance state.
Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places the driver
differential outputs in a high impedance state.
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high. A logic high on DI forces
A high and B low.
Ground Connection, 0 V.
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
Power Supply, 5 V ± 10%.
Table 5. Selection Table
Part No.
ADM483E
Duplex
Half
Data Rate (kbps)
250
Low Power Shutdown
Yes
Tx/Rx Enable
Yes
I
CC
(μA)
36
No. of Tx/Rx on Bus
32
ESD kV
±15
Rev. A | Page 6 of 16
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