ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
V
CC
R
L
= 110Ω
S1
0V OR 3V
D
C
L
= 50pF
2
GENERATOR
1
50Ω
OUT
V
ID
GENERATOR
1
50Ω
R
OUT
C
L
= 15pF
2
1.5V
0V
1
PPR = 250kHz, 50% DUTY CYCLE,
t
≤
6.0ns, Z = 50Ω.
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
V
OM
=
V
CC
2
1
PPR = 250kHz, 50% DUTY CYCLE,
t
≤
6.0ns, Z = 50Ω.
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
3V
IN
1.5V
1.5V
0V
3V
IN
1.5V
1.5V
0V
t
PSL
OUT
V
OM
t
PLZ
V
CC
0.25V
06284-013
t
RPLH
V
OM
t
RPHL
V
CC
V
OM
0V
06284-014
V
OL
OUT
Figure 13. Driver Enable and Disable Times (t
PZL
, t
PSL
, t
PLZ
)
Figure 14. Receiver Propagation Delays
+1.5V
–1.5V
S3
V
ID
R
C
L2
GENERATOR
1
1kΩ
S1
V
CC
S2
50Ω
1
PPR = 250kHz, 50% DUTY CYCLE,
t
≤
6.0ns, Z = 50Ω.
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
+3V
IN
+1.5V
t
RPZH
t
RPSH
OUT
+1.5V
0V
V
OH
S1 OPEN
S2 CLOSED
S3 = +1.5V
+3V
IN
+1.5V
t
RPZL
t
RPSL
OUT
+1.5V
0V
S1 CLOSED
S2 OPEN
S3 = –1.5V
V
CC
V
OL
0V
+3V
IN
+1.5V
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
+3V
IN
+1.5V
0V
S1 CLOSED
S2 OPEN
S3 = –1.5V
t
RPHZ
OUT
+0.25V
V
OH
OUT
0V
+0.25V
t
RPLZ
V
CC
V
OL
Figure 15. Receiver Enable and Disable Times
Rev. A | Page 10 of 20
06284-015
AD [ ANALOG DEVICES ]
