ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
V
CC
R
= 110ꢀ
L
S1
OUT
OUT
0V OR 3V
D
V
ID
R
1
GENERATOR
2
C
= 50pF
50ꢀ
L
2
C
= 15pF
L
1
GENERATOR
50ꢀ
1.5V
0V
V
CC
V
=
OM
2
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
1
2
O
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
C
INCLUDES PROBE AND STRAY CAPACITANCE.
3V
0V
3V
0V
IN
1.5V
1.5V
1.5V
1.5V
IN
tPSL
tPLZ
tRPLH
tRPHL
V
V
CC
OUT
V
V
CC
OM
0.25V
V
V
OM
OUT
OM
OL
0V
Figure 13. Driver Enable and Disable Times (tPZL, tPSL, tPLZ
)
Figure 14. Receiver Propagation Delays
S1
S2
S3
+1.5V
–1.5V
V
CC
1kꢀ
V
ID
R
2
C
L
1
GENERATOR
50ꢀ
1
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
2
C
INCLUDES PROBE AND STRAY CAPACITANCE.
+3V
+3V
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
+1.5V
IN
+1.5V
IN
0V
V
tRPZL
tRPSL
tRPZH
tRPSH
V
OH
CC
OUT
OUT
+1.5V
+1.5V
0V
V
OL
+3V
0V
+3V
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
+1.5V
+1.5V
IN
IN
tRPHZ
tRPLZ
V
V
OH
CC
OL
OUT
OUT
+0.25V
0V
V
+0.25V
Figure 15. Receiver Enable and Disable Times
Rev. A | Page 10 of 20
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